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US4631493A Expired / Lapsed US ⏱️ 0.0 years remaining

Circuit for DC biasing

Assignee: Eaton Corp
•
Filing: 1985-03-18
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Granted: 1986-12-23
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Expires: 2005-03-18
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Abstract

Abstract The present invention includes an apparatus and a method for connecting at least a pair of stages in DC series between a pair of power-supply potentials so as to provide economical utilization of the power supply. The stages are connected so as to maintain their AC independence.

Inventors

  • 👤 George D. Vendelin
  • 👤 Behruz Rezvani

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-11-03 21:04
CPC Classifications
H; H03; H03F; H03F3/00; H03F3/189; H03F3/19; H03F3/193; H03F3/1935; H03F1/00; H03F1/02; H03F1/0205; H03F1/0283; H03F3/60; H03F3/605; H03F3/607; H03F3/68

Claims Analysis

Total Claims: 8
Claim 1
Independent Claim 141 words
The combination comprising: a first stage for connection to at least one of a pair of power-supply potentials; and a second stage for connection to at least the other one of said pair of power-supply potentials, said second stage including, a field-effect transistor having a drain, a source, and a gate, means for coupling said drain of said second-stage transistor to said other one of said pair of power-supply potentials, means for DC coupling said source of said second-stage transistor to said first stage and for AC decoupling said source of said second-stage transistor from said first stage, and means for biasing said gate of said second-stage transistor at a predetermined DC potential which is independent of the level of the DC current which flows through said second-stage transistor establishing the DC potential developed at said source of said second-stage transistor.
Claim 2
Dependent Claim 141 words
The combination comprising: a first stage for connection to at least one of a pair of power-supply potentials; and a second stage for connection to at least the other one of said pair of power-supply potentials, said second stage including, a field-effect transistor having a drain, a source, and a gate, means for coupling said drain of said second-stage transistor to said other one of said pair of power-supply potentials, means for DC coupling said source of said second-stage transistor to said first stage and for AC decoupling said source of said second-stage transistor from said first stage, and means for biasing said gate of said second-stage transistor at a predetermined DC potential which is independent of the level of the DC current which flows through said second-stage transistor establishing the DC potential developed at said source of said second-stage transistor.
Claim 3
Dependent Claim 32 words
The combination as recited in claim 1 wherein said second stage DC coupling and AC decoupling means has a bypassing capacitor connected between said source of said second-stage transistor and circuit ground.
Claim 4
Dependent Claim 29 words
The combination as recited in claim 1 wherein said DC coupling and AC decoupling means has a line connecting said source of said second-stage transistor to said first stage.
Claim 5
Dependent Claim 32 words
The combination as recited in claim 3 wherein said second stage DC coupling and AC decoupling means has a bypassing capacitor connected between said source of said second-stage transistor and circuit ground.
Claim 6
Dependent Claim 82 words
The combination as recited in claim 1 wherein said first stage includes: a field-effect transistor having a gate, a drain, and a source; means for biasing said gate of said first-stage transistor at a predetermined DC potential; means for coupling said drain of said first-stage transistor to said second stage; and source-biasing means for establishing the DC current which flows through said first-stage transistor, said current forming at least a predetermined portion of the DC current which flows through said second stage.
Claim 7
Dependent Claim 35 words
The combination as recited in claim 5 wherein said first-stage source-biasing means has a resistor connected to said source of said first-stage transistor and for connection to said one of said pair of power-supply potentials.
Claim 8
Dependent Claim 27 words
The combination as recited in claim 6 wherein said first stage further includes a bypassing capacitor connected between said source of said first-stage transistor and circuit ground.

References Cited (Backward Citations)

CA652137A Cited
FR1238817A Cited
DE1277356B Cited
DE1240131B Cited
US4496909A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1989-12-22 1990-06-23 1990-12-23 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1993-12-22 1994-06-23 1994-12-23 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1997-12-22 1998-06-23 1998-12-23 $7700.00 Window Closed / Lapsed

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