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US6400007B1 Expired / Lapsed US ⏱️ 0.0 years remaining

Stacked structure of semiconductor means and method for manufacturing the same

Assignee: Kingpak Technology Inc
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Filing: 2001-04-16
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Granted: 2002-06-04
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Expires: 2021-04-16
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Abstract

Abstract An stacked structure of semiconductor means and method for manufacturing the same, comprises a substrate, a lower semiconductor chip, an adhered glue layer, a plurality of wires and an upper semiconductor chip. The adhered glue layer located between the substrate and the lower semiconductor to adhere the lower semiconductor to the substrate. The overflow glue of the adhered glue layer covered above the periphery of the lower semiconductor chip. The plurality of wires each being electrically connected to the lower semiconductor chip and the substrate, so that each wires are located above the overflow glue. The upper semiconductor chip is located above lower semiconductor chip and electrically connected to the substrate.

Inventors

  • 👤 Jichen Wu
  • 👤 Meng Ru Tsai
  • 👤 Nai Hua Yeh
  • 👤 Chen Pin Peng

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-11-09 11:24
CPC Classifications
H; H10; H10W; H10W72/00; H10W72/30; H10W74/00; H10W74/10; H10W74/111; H10W74/114; H10W74/117; H10W90/00; H10W72/01; H10W72/013; H10W72/01308; H10W72/071; H10W72/073; H10W72/07311; H10W72/075; H10W72/50; H10W72/551; H10W72/851; H10W72/874; H10W72/884; H10W72/90; H10W72/951; H10W90/20; H10W90/231; H10W90/291; H10W90/701; H10W90/731; H10W90/732; H10W90/734; H10W90/751; H10W90/754

Claims Analysis

Total Claims: 13
Claim 1
Independent Claim 216 words
A stacked structure of semiconductor means used for electrically connecting to a printed circuit board, comprising: a substrate having a first surface and a second surface opposite to the first surface, the first surface formed with signal input terminals, then, the second surface formed with signal output terminals for electrically connected to the printed circuit board; a lower semiconductor chip having a upper surface and a lower surface, the central part of the upper surface formed with a plurality of bonding pads; an adhered glue layer located between the substrate and the lower semiconductor for adhering the lower surface of the semiconductor to the first surface of the substrate, the overflow glue of the adhered glue layer covered above the periphery of the lower semiconductor chip; a plurality of wires each having a first end and second end away from the first end, the first end being electrically connected to the bonding pads of the lower semiconductor chip, the second end being electrically connected to the signal input terminals so that signals from the lower semiconductor chip are capable of being transmitted to the substrate, an upper semiconductor chip located on the upper surface of the semiconductor chip to stack above the lower semiconductor chip and electrically connected to the signal input terminals of the substrate.
Claim 2
Dependent Claim 216 words
A stacked structure of semiconductor means used for electrically connecting to a printed circuit board, comprising: a substrate having a first surface and a second surface opposite to the first surface, the first surface formed with signal input terminals, then, the second surface formed with signal output terminals for electrically connected to the printed circuit board; a lower semiconductor chip having a upper surface and a lower surface, the central part of the upper surface formed with a plurality of bonding pads; an adhered glue layer located between the substrate and the lower semiconductor for adhering the lower surface of the semiconductor to the first surface of the substrate, the overflow glue of the adhered glue layer covered above the periphery of the lower semiconductor chip; a plurality of wires each having a first end and second end away from the first end, the first end being electrically connected to the bonding pads of the lower semiconductor chip, the second end being electrically connected to the signal input terminals so that signals from the lower semiconductor chip are capable of being transmitted to the substrate, an upper semiconductor chip located on the upper surface of the semiconductor chip to stack above the lower semiconductor chip and electrically connected to the signal input terminals of the substrate.
Claim 3
Dependent Claim 32 words
The stacked structure of a semiconductor means according to claim 1 , wherein the signals output terminals of the substrate are metallic balls arranged in the form of a ball grid array.
Claim 4
Dependent Claim 52 words
The stacked structure of a semiconductor means according to claim 1 , wherein a projecting element is formed on the periphery of the first surface of the substrate to stop the overflow glue of the adhered glue resin. Thus the overflow glue covered above the upper surface of the lower semiconductor chip.
Claim 5
Dependent Claim 19 words
The stacked structure of a semiconductor means according to claim 3 , wherein the projecting element is a dam.
Claim 6
Dependent Claim 33 words
The stacked structure of a semiconductor means according to claim 1 , wherein the upper semiconductor chip being electrically connected to the signal input terminals of the substrate by a plurality of wires.
Claim 7
Dependent Claim 39 words
The stacked structure of a semiconductor means according to claim 1 , wherein a package layer provided on the lower semiconductor chip and the upper semiconductor chip for preventing the lower semiconductor chip, the upper semiconductor chip and wires.
Claim 8
Independent Claim 204 words
A method for manufacturing a stacked structure of semiconductor means, comprising the steps: providing a substrate having a first surface and a second surface opposite to the first surface, the first surface formed with signal input terminals, then, the second surface formed with signal output terminals; providing a lower semiconductor chip having an upper surface and a lower surface, a plurality of pads arranged on the central of the upper surface of the lower semiconductor chip; placing a adhered glue layer between the lower surface of the lower semiconductor chip and the upper surface of the substrate for adhering the lower semiconductor chip to the substrate, so that the overflow glue of the adhered glue layer covered above the upper surface of the lower semiconductor chip; providing a plurality of wires having a first end and second end, the first end being electrically connected to the pads of the lower semiconductor chip, and the second end electrically connected to the signal input terminal of the substrate; and placing an upper semiconductor chip over the upper surface of the lower semiconductor chip to formed stacked with lower semiconductor chip, and the upper semiconductor chip being electrically connected to the signal input terminal of the substrate.
Claim 9
Independent Claim 204 words
A method for manufacturing a stacked structure of semiconductor means, comprising the steps: providing a substrate having a first surface and a second surface opposite to the first surface, the first surface formed with signal input terminals, then, the second surface formed with signal output terminals; providing a lower semiconductor chip having an upper surface and a lower surface, a plurality of pads arranged on the central of the upper surface of the lower semiconductor chip; placing a adhered glue layer between the lower surface of the lower semiconductor chip and the upper surface of the substrate for adhering the lower semiconductor chip to the substrate, so that the overflow glue of the adhered glue layer covered above the upper surface of the lower semiconductor chip; providing a plurality of wires having a first end and second end, the first end being electrically connected to the pads of the lower semiconductor chip, and the second end electrically connected to the signal input terminal of the substrate; and placing an upper semiconductor chip over the upper surface of the lower semiconductor chip to formed stacked with lower semiconductor chip, and the upper semiconductor chip being electrically connected to the signal input terminal of the substrate.
Claim 10
Dependent Claim 36 words
The method for manufacturing a stacked structure of a semiconductor means according to claim 7 , wherein the signal output terminals of the substrate are metallic balls arranged in the form of a ball grid array.
Claim 11
Dependent Claim 57 words
The method for manufacturing a stacked structure of a semiconductor means according to claim 7 , wherein a projecting element is formed on the periphery of the first surface of the substrate to stop the overflow glue of the adhered glue resin. So that the overflow glue is covered the upper surface of the lower semiconductor chip.
Claim 12
Dependent Claim 23 words
The method for manufacturing a stacked structure of a semiconductor means according to claim 9 , wherein the projecting element is a dam.
Claim 13
Dependent Claim 42 words
The method for manufacturing a stacked structure of a semiconductor means according to claim 7 , wherein a package layer provided on the lower semiconductor chip and the upper semiconductor chip for preventing the lower semiconductor chip and the upper semiconductor chip.

References Cited (Backward Citations)

USRE36613E Cited
US5804874A Cited
US6087718A Cited
US6271598B1 Cited
US6100594A Cited
US6180881B1 Cited
US6316727B1 Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 2005-06-03 2005-12-03 2006-06-04 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 2009-06-03 2009-12-03 2010-06-04 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2013-06-03 2013-12-03 2014-06-04 $7700.00 Window Closed / Lapsed

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