Zero hold time circuit for high speed bus applications

Claim 2

A zero hold time input data cell comprising: an input pad; an input buffer circuit connected to the input pad that receives an input data signal from the input pad; a circuit element; and a delay circuit connected to the input buffer circuit, the delay circuit having a plurality of delay stages, the plurality of delay stages having a plurality of outputs such that each delay stage has an output that is connectable to the circuit element, none of the outputs being connected together.

Claim 3

The cell of claim 1 wherein the input buffer is non-inverting.

Claim 4

The cell of claim 1 wherein the input buffer is inverting.

Claim 5

The cell of claim 3 and further comprising an inverter connected to the delay circuit.

Claim 6

The cell of claim 1 wherein each delay stage includes: a first inverter; a second inverter connected to the first inverter; and a capacitive load connected to the first inverter.

Claim 7

The cell of claim 5 wherein the capacitive load includes a transistor.

Claim 8

The circuit of claim 1 wherein each delay stage provides a delay, and wherein the delay provided by each delay stage is substantially constant.

Claim 9

The circuit of claim 7 wherein the delay provided by each stage has a first delay when process, voltage, and temperature conditions have a first value, and a second delay when process, voltage, and temperature conditions have a second value that is greater than the first value, the first delay being greater than the second delay.

Claim 10

An integrated circuit comprising: a zero hold time input data cell having: an input data pad; an input buffer circuit connected to the input data pad that receives an input data signal from the input data pad; a delay latch; a delay circuit connected to the input buffer circuit, the delay circuit having a plurality of delay stages, the plurality of delay stages having a plurality of outputs such that each delay stage has an output that is connectable to the delay latch, none of the outputs being connected together; and a clock input cell having: a clock pad; an input clock circuit connected to the clock pad and the delay latch; and a data flip flop connected to the delay latch and the input clock circuit.

Claim 11

An integrated circuit comprising: a zero hold time input data cell having: an input data pad; an input buffer circuit connected to the input data pad that receives an input data signal from the input data pad; a delay latch; a delay circuit connected to the input buffer circuit, the delay circuit having a plurality of delay stages, the plurality of delay stages having a plurality of outputs such that each delay stage has an output that is connectable to the delay latch, none of the outputs being connected together; and a clock input cell having: a clock pad; an input clock circuit connected to the clock pad and the delay latch; and a data flip flop connected to the delay latch and the input clock circuit.

Claim 12

The circuit of claim 9 wherein the input buffer is non-inverting.

Claim 13

The circuit of claim 9 wherein the input buffer is inverting.

Claim 14

The circuit of claim 11 further comprising an inverter connected to the delay circuit.

Claim 15

The circuit of claim 9 wherein each delay stage includes: a first inverter; a second inverter connected to the first inverter; and a capacitive load connected to the first inverter.

Claim 16

The circuit of claim 9 wherein the input clock circuit includes a hierarchical clock tree.

Claim 21

A zero hold time input data cell comprising: an input pad; an input buffer circuit connected to the input pad that receives an input data signal from the input pad; a circuit element; and a delay circuit connected to the input buffer circuit, the delay circuit having a plurality of delay stages, the plurality of delay stages having a plurality of outputs such that each delay stage has an output that is connectable to the circuit element, none of the outputs being connected together, each delay stage providing a delay, the delay provided by each delay stage being substantially constant, the delay provided by each delay stage having a first delay when process, temperature, and voltage conditions have a first value, and a second delay when process, temperature, and voltage conditions have a second value that is greater than the first value, the first delay being greater than the second delay, the first delay being approximately 2.3 times greater than the second delay.

Claim 22

A zero hold time input data cell comprising: an input pad; an input buffer circuit connected to the input pad that receives an input data signal from the input pad; a circuit element; and a delay circuit connected to the input buffer circuit, the delay circuit having a plurality of delay stages, the plurality of delay stages having a plurality of outputs such that each delay stage has an output that is connectable to the circuit element, none of the outputs being connected together, each delay stage providing a delay, the delay provided by each delay stage being substantially constant, the delay provided by each delay stage having a first delay when process, temperature, and voltage conditions have a first value, and a second delay when process, temperature, and voltage conditions have a second value that is greater than the first value, the first delay being greater than the second delay, the first delay being approximately 2.3 times greater than the second delay.

Claim 23

A zero hold time input data cell comprising: an input pad; an input buffer circuit connected to the input pad that receives an input data signal from the input pad; a circuit element, the circuit element being a latch having a data input and a latching input, the latching input being responsive to a falling edge; and a delay circuit connected to the input buffer circuit, the delay circuit having a plurality of delay stages, the plurality of delay stages having a plurality of outputs such that each delay stage has an outfit that is connectable to the circuit element, none of the outputs being connected together.

Claim 24

A zero hold time input data cell comprising: an input pad; an input buffer circuit connected to the input pad that receives an input data signal from the input pad; a circuit element, the circuit element being a latch having a data input and a latching input, the latching input being responsive to a falling edge; and a delay circuit connected to the input buffer circuit, the delay circuit having a plurality of delay stages, the plurality of delay stages having a plurality of outputs such that each delay stage has an outfit that is connectable to the circuit element, none of the outputs being connected together.

Claim 25

A zero hold time input data cell comprising: an input pad; an input buffer circuit connected to the input pad that receives an input data signal from the input pad; a circuit element, the circuit element being a flip flop having a data input and a clock input that receives a clock signal, the clock input being responsive to a rising edge of the clock signal; and a delay circuit connected to the input buffer circuit, the delay circuit having a plurality of delay stages, the plurality of delay stages having a plurality of outputs such that each delay stage has an output that is connectable to the circuit element, none of the outputs being connected together.

Claim 26

A zero hold time input data cell comprising: an input pad; an input buffer circuit connected to the input pad that receives an input data signal from the input pad; a circuit element, the circuit element being a flip flop having a data input and a clock input that receives a clock signal, the clock input being responsive to a rising edge of the clock signal; and a delay circuit connected to the input buffer circuit, the delay circuit having a plurality of delay stages, the plurality of delay stages having a plurality of outputs such that each delay stage has an output that is connectable to the circuit element, none of the outputs being connected together.

Claim 27

A zero hold time input data cell comprising: an input pad; an input buffer circuit connected to the input pad that receives an input data signal from the input pad; a circuit element, the circuit element being a latch having a data input, a clock input that receives a clock signal, and a data output, the clock input being responsive to a falling edge of the clock signal, and further comprising a flip flop having a data input connected to the data output and a clock input that receives the clock signal, the clock input of the flip flop being responsive to a rising edge of the clock signal; and a delay circuit connected to the input buffer circuit, the delay circuit having a plurality of delay stages, the plurality of delay stages having a plurality of outputs such that each delay stage has an output that is connectable to the circuit element, none of the outputs being connected together.

Claim 28

A zero hold time input data cell comprising: an input pad; an input buffer circuit connected to the input pad that receives an input data signal from the input pad; a circuit element, the circuit element being a latch having a data input, a clock input that receives a clock signal, and a data output, the clock input being responsive to a falling edge of the clock signal, and further comprising a flip flop having a data input connected to the data output and a clock input that receives the clock signal, the clock input of the flip flop being responsive to a rising edge of the clock signal; and a delay circuit connected to the input buffer circuit, the delay circuit having a plurality of delay stages, the plurality of delay stages having a plurality of outputs such that each delay stage has an output that is connectable to the circuit element, none of the outputs being connected together.

Claim 29

An input data cell comprising: a circuit element; a data pad; an input buffer connected to the data pad and a buffered node; a programmable delay circuit connected to the buffered node, the programmable delay circuit having a plurality of delay stages, the plurality of delay stages having a plurality of output nodes such that each delay stage has an output node, each output node being connectable to the circuit element.

Claim 30

An input data cell comprising: a circuit element; a data pad; an input buffer connected to the data pad and a buffered node; a programmable delay circuit connected to the buffered node, the programmable delay circuit having a plurality of delay stages, the plurality of delay stages having a plurality of output nodes such that each delay stage has an output node, each output node being connectable to the circuit element.

Claim 31

The input data cell of claim 21 wherein each delay stage has an input node and an output node such that, except for a first delay stage, the input node of each stage is connected to the output node of a preceding delay stage.

Claim 32

The input data cell of claim 21 wherein the buffered node is connectable to the circuit element.

Claim 33

The input data cell of claim 21 wherein each data stage includes: a first inverter having an inverter output; a second inverter having an inverter input connected to the inverter output of the first inverter; and a capacitive load connected to the inverter output of the first inverter.

Claim 34

The input data cell of claim 24 wherein the clock circuit includes a hierarchical clock tree.

Claim 35

The input data cell of claim 21 and further comprising: a clock pad; and a clock circuit connected to the clock pad and the circuit element.

Claim 36

An input data cell comprising: a data pad; an input buffer connected to the data pad and a buffered node; a programmable delay circuit connected to the buffered node, the programmable delay circuit having a plurality of delay stages, each delay stage having an input node and an output node such that, except for a first delay stage, the input node of each stage is connected to the output node of a preceding delay stage; and a circuit element connected to an output node.

Claim 37

An input data cell comprising: a data pad; an input buffer connected to the data pad and a buffered node; a programmable delay circuit connected to the buffered node, the programmable delay circuit having a plurality of delay stages, each delay stage having an input node and an output node such that, except for a first delay stage, the input node of each stage is connected to the output node of a preceding delay stage; and a circuit element connected to an output node.

Claim 38

The input data cell of claim 27 wherein each data stage includes: a first inverter having an inverter output; a second inverter having an inverter input connected to the inverter output of the first inverter; and a capacitive load connected to the inverter output of the first inverter.

Claim 39

The input data cell of claim 27 and further comprising: a clock pad; and a clock circuit connected to, the clock pad and the circuit element.

Claim 40

The input data cell of claim 29 wherein the clock circuit includes a hierarchical clock tree.