Patent US6389558B1 successfully refreshed from Google Patents.
US6389558B1
Expired / Lapsed
US
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Embedded logic analyzer for a programmable logic device
Assignee: Altera Corp
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Filing: 2000-07-06
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Granted: 2002-05-14
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Expires: 2020-07-06
Abstract
Abstract A technique for embedding a logic analyzer in a programmable logic device allows debugging of such a device in its actual operating conditions. A logic analyzer circuit is embedded within a PLD, it captures and stores logic signals, and it unloads these signals through an interface to be viewed on a computer. Using an electronic design automation (EDA) software tool running on a computer system, an engineer specifies signals of the PLD to be monitored, specifies the number of samples to be stored, and specifies a system clock signal and a trigger condition that will begin the acquisition of data. The EDA tool then automatically inserts the logic analyzer circuit into the electronic design of the PLD which is compiled and downloaded to configure the PLD. Using an interface connected between the PLD and the computer, the EDA tool communicates with the embedded logic analyzer in order to arm the circuit and to poll it until an acquisition has been made. The EDA tool then directs the logic analyzer to unload the data from its capture buffer and then displays the data on the computer. The logic analyzer circuit may then be rearmed to capture another sequence of sample values. The trigger condition may be changed without recompiling. The design may be recompiled with new logic analyzer parameters to debug a different portion.
Inventors
- 👤 Alan L. Herrmann
- 👤 Greg P. Nugent
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 02:01
CPC Classifications
G; G06; G06F; G06F8/00; G06F8/60; G01; G01R; G01R31/00; G01R31/28; G01R31/317; G01R31/3177; G01R31/3181; G01R31/3185; G01R31/318516; G06F11/00; G06F11/07; G06F11/0703; G06F11/0706; G06F11/0748; G06F11/22; G06F11/2294; G06F30/00; G06F30/30; G06F30/32; G06F30/33; G06F30/3308; G06F30/331; G06F30/34; G06F30/347; G06F8/65; G06F8/70; G06F8/71; G06Q; G06Q10/00; G06Q10/06; G06Q10/10; G06F2111/00; G06F2111/02; Y; Y10; Y10S; Y10S707/00; Y10S707/99951; Y10S707/99952; Y10S707/99953; Y10S707/99954
Claims Analysis
Total Claims: 32
Claim 1
Independent Claim
77 words
A programmable logic development system arranged to debug a programmable logic device (PLD), said system comprising: a PLD including a logic analyzer integrated with user logic, and interface pins; a computer having software arranged to deliver control signals to said integrated logic analyzer via said interface pins; and a communication medium in electrical communication between said computer and said interface pins of said PLD, said communication medium being arranged to deliver said control signals to said PLD.
Claim 2
Dependent Claim
77 words
A programmable logic development system arranged to debug a programmable logic device (PLD), said system comprising: a PLD including a logic analyzer integrated with user logic, and interface pins; a computer having software arranged to deliver control signals to said integrated logic analyzer via said interface pins; and a communication medium in electrical communication between said computer and said interface pins of said PLD, said communication medium being arranged to deliver said control signals to said PLD.
Claim 3
Dependent Claim
17 words
A system as recited in claim 1 wherein said PLD is a field programmable gate array (FPGA).
Claim 4
Dependent Claim
49 words
A system as recited in claim 1 wherein said integrated logic analyzer includes a trigger register for storing a trigger condition, and wherein said control signals include signals arranged to modify said trigger condition, whereby said trigger condition may be modified by said user without recompiling said user logic.
Claim 5
Dependent Claim
18 words
A system as recited in claim 1 further comprising: a circuit board on which is mounted said PLD.
Claim 6
Dependent Claim
50 words
A system as recited in claim 1 wherein said PLD further includes control logic arranged to communicate between said integrated logic analyzer and said interface pins of said PLD, wherein said control signals are delivered to said integrated logic analyzer via said control logic as well as said interface pins.
Claim 7
Dependent Claim
14 words
A system as recited in claim 1 wherein said communication medium is a cable.
Claim 8
Dependent Claim
34 words
A system as recited in claim 6 whereby internal signals of said user logic are captured by said integrated logic analyzer and transmitted to said computer via said cable for viewing by a user.
Claim 9
Independent Claim
97 words
A method of compiling a logic analyzer along with an electronic design for a programmable logic device (PLD), said method comprising: receiving an electronic design for a programmable logic device (PLD), said electronic design including a plurality of internal signal lines; receiving a representation of a logic analyzer to be integrated with said electronic design; connecting selected internal signal lines of said electronic design to inputs of said logic analyzer; and a step of performing the function of compiling said electronic design along with said logic analyzer to produce a compiled design suitable for programming said PLD.
Claim 10
Independent Claim
97 words
A method of compiling a logic analyzer along with an electronic design for a programmable logic device (PLD), said method comprising: receiving an electronic design for a programmable logic device (PLD), said electronic design including a plurality of internal signal lines; receiving a representation of a logic analyzer to be integrated with said electronic design; connecting selected internal signal lines of said electronic design to inputs of said logic analyzer; and a step of performing the function of compiling said electronic design along with said logic analyzer to produce a compiled design suitable for programming said PLD.
Claim 11
Dependent Claim
32 words
A method as recited in claim 8 , whereby said logic analyzer is arranged to store data from said selected internal signal lines when said compiled design is downloaded to said PLD.
Claim 12
Independent Claim
94 words
A method of compiling a logic analyzer along with an electronic design for a programmable logic device (PLD), said method comprising: receiving an electronic design for a programmable logic device (PLD), said electronic design including a plurality of internal signal lines; producing a representation of a logic analyzer to be integrated with said electronic design; modifying said electronic design to include said logic analyzer; connecting selected internal signal lines of said electronic design to inputs of said logic analyzer; and compiling said modified electronic design to produce a compiled design for programming said PLD.
Claim 13
Independent Claim
94 words
A method of compiling a logic analyzer along with an electronic design for a programmable logic device (PLD), said method comprising: receiving an electronic design for a programmable logic device (PLD), said electronic design including a plurality of internal signal lines; producing a representation of a logic analyzer to be integrated with said electronic design; modifying said electronic design to include said logic analyzer; connecting selected internal signal lines of said electronic design to inputs of said logic analyzer; and compiling said modified electronic design to produce a compiled design for programming said PLD.
Claim 14
Dependent Claim
17 words
A method as recited in claim 10 wherein said PLD is a field programmable gate array (FPGA).
Claim 15
Dependent Claim
37 words
A method as recited in claim 10 wherein said logic analyzer includes a trigger register for storing a trigger condition, and wherein said trigger condition may be modified by a user without recompiling said modified electronic design.
Claim 16
Dependent Claim
28 words
A method as recited in claim 10 wherein said modified electronic design includes control logic arranged to communicate between said logic analyzer and interface pins of said PLD.
Claim 17
Dependent Claim
23 words
A method as recited in claim 10 wherein said electronic design and said logic analyzer are represented using a hardware description language (HDL).
Claim 18
Dependent Claim
29 words
A method as recited in claim 10 wherein said step of compiling includes the sub-steps of: synthesizing said modified electronic design; and placing and routing said modified electronic design.
Claim 19
Dependent Claim
71 words
A method as recited in claim 10 further comprising: receiving a name of a trigger signal, said trigger signal corresponding to one of said internal signals; connecting said trigger signal to a trigger input of said logic analyzer, such that when said compiled design is downloaded to said PLD and said trigger signal matches a trigger condition said logic analyzer is arranged to begin storing data from said selected internal signals.
Claim 20
Dependent Claim
74 words
A method as recited in claim 10 , wherein said logic analyzer includes a first trigger condition, said method further comprising: programming said PLD with said compiled design; and sending a second trigger condition to said logic analyzer integrated within said PLD to replace said first trigger condition without recompiling said modified electronic design, whereby said logic analyzer is arranged to begin monitoring said selected internal signals upon occurrence of said second trigger condition.
Claim 21
Dependent Claim
96 words
A method as recited in claim 10 , wherein said selected internal signals include original signals, said method further comprising: programming said PLD with said compiled design such that said logic analyzer is integrated within said PLD; receiving names of new internal signals, said new internal signals being different from said original internal signals; recompiling said modified electronic design such that said new internal signals are connected to said inputs of said logic analyzer; and reprogramming said PLD with said recompiled modified electronic design, whereby said logic analyzer is arranged to monitor said new internal signals.
Claim 22
Dependent Claim
32 words
A method as recited in claim 10 , whereby said logic analyzer is arranged to store data from said selected internal signal lines when said compiled design is downloaded to said PLD.
Claim 23
Independent Claim
105 words
A method of retrieving data stored in a logic analyzer integrated within a logic device, said method comprising: compiling an electronic design which includes a logic analyzer; programming a logic device with said compiled electronic design, said logic analyzer being integrated within said logic device; arming said logic analyzer in said logic device such that said logic analyzer is arranged to capture internal signals of said logic device; issuing a command to said logic analyzer in said logic device to transfer said captured signals; and receiving said captured internal signals from said logic analyzer such that said signals may be displayed on a user computer.
Claim 24
Independent Claim
105 words
A method of retrieving data stored in a logic analyzer integrated within a logic device, said method comprising: compiling an electronic design which includes a logic analyzer; programming a logic device with said compiled electronic design, said logic analyzer being integrated within said logic device; arming said logic analyzer in said logic device such that said logic analyzer is arranged to capture internal signals of said logic device; issuing a command to said logic analyzer in said logic device to transfer said captured signals; and receiving said captured internal signals from said logic analyzer such that said signals may be displayed on a user computer.
Claim 25
Dependent Claim
18 words
A method as recited in claim 20 wherein said logic device is a field programmable gate array (FPGA).
Claim 26
Dependent Claim
37 words
A method as recited in claim 20 wherein said logic analyzer includes a trigger register that stores a trigger condition, said method further comprising: issuing a command to modify said trigger condition without recompiling said electronic design.
Claim 27
Dependent Claim
23 words
A method as recited in claim 20 wherein said electronic design and said logic analyzer are represented using a hardware description language (HDL).
Claim 28
Dependent Claim
17 words
A method as recited in claim 20 wherein said logic device is a programmable logic device (PLD).
Claim 29
Dependent Claim
102 words
A programmable logic device (PLD) comprising: user circuitry representing one iteration of an electronic design in a design process to create a final PLD, said user circuitry including interior circuitry that is not directly connected to I/O pins of said PLD; logic analyzer circuitry integrated within said PLD such that a portion of said interior circuitry is connected to said logic analyzer circuitry; and control logic arranged to communicate between said integrated logic analyzer and said pins of said PLD, whereby said integrated logic analyzer is arranged to capture data from said interior circuitry and to communicate said data via said pins.
Claim 30
Dependent Claim
102 words
A programmable logic device (PLD) comprising: user circuitry representing one iteration of an electronic design in a design process to create a final PLD, said user circuitry including interior circuitry that is not directly connected to I/O pins of said PLD; logic analyzer circuitry integrated within said PLD such that a portion of said interior circuitry is connected to said logic analyzer circuitry; and control logic arranged to communicate between said integrated logic analyzer and said pins of said PLD, whereby said integrated logic analyzer is arranged to capture data from said interior circuitry and to communicate said data via said pins.
Claim 31
Dependent Claim
17 words
A PLD as recited in claim 25 wherein said PLD is a field programmable gate array (FPGA).
Claim 32
Dependent Claim
36 words
A PLD as recited in claim 25 wherein said logic analyzer includes a trigger register for storing a trigger condition, and wherein said trigger condition may be modified by a user without recompiling said electronic design.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2005-05-13 | 2005-11-12 | 2006-05-14 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2009-05-13 | 2009-11-12 | 2010-05-14 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2013-05-13 | 2013-11-12 | 2014-05-14 | $7700.00 | Window Closed / Lapsed |