Patent US5659263A successfully refreshed from Google Patents.
Patent US6384652B1 successfully refreshed from Google Patents.
US6384652B1
Expired / Lapsed
US
⏱️ 0.0 years remaining
Clock duty cycle correction circuit
Assignee: Taiwan Semiconductor Manufacturing Co TSMC Ltd
•
Filing: 2000-08-17
•
Granted: 2002-05-07
•
Expires: 2020-08-17
Abstract
Abstract A duty cycle correcting circuit is described having a first capacitor connected between a first node and a reference node and a second capacitor connected between a second node and the reference node. When the duty cycle of the output clock signal is greater than 50% the voltage across the second capacitor decreases thereby increasing the charging rate of the first capacitor, decreasing the discharging rate of the first capacitor, and restoring the output duty cycle to 50%. When the duty cycle of the output clock signal is less than 50% the voltage across the second capacitor increases thereby decreasing the charging rate of the first capacitor, increasing the discharging rate of the first capacitor, any restoring output duty cycle to 50%.
Inventors
- 👤 Tzi-Hsiung Shu
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 18:51
CPC Classifications
H; H03; H03K; H03K5/00; H03K5/156; H03K5/1565; H03K2005/00013; H03K2005/00019; H03K2005/00026; H03K2005/00032; H03K2005/00039
Claims Analysis
Total Claims: 20
Claim 1
Independent Claim
340 words
A clock duty cycle correction circuit, comprising: an input node, wherein the voltage between said input node and ground is either at a high voltage level or a low voltage level; an output node, a first node, a second node, and a reference node; a first capacitor connected between said first node and said reference node; a second capacitor connected between said second node and said reference node; means for charging said first capacitor at a rate which varies inversely with the voltage drop from said second node to said reference node when the voltage between said input node and ground is said low voltage level; means for discharging said first capacitor at a rate which varies directly with the voltage drop from said second node to said reference node when the voltage between said input node and ground is said high voltage level; means for producing said low voltage level between said output node and ground when the voltage drop from said first node to said reference node is greater than a threshold voltage and said high voltage level between said output node and ground when the voltage drop from said first node to said reference node is less than said threshold voltage, wherein said means for producing said low voltage level between said output node and ground when the voltage drop from said first node to said reference node is greater than a threshold voltage and said high voltage level between said output node and ground when the voltage drop from said first node to said reference node is less than said threshold voltage comprises an inverter, wherein said inverter is used as a comparator, said inverter comprising a P channel metal oxide semiconductor field effect transistor and an N channel metal oxide semiconductor field effect transistor; means for charging said second capacitor when the voltage between said output node and ground is said low voltage level; and means for discharging said second capacitor when the voltage between said output node and ground is said high voltage level.
Claim 2
Dependent Claim
340 words
A clock duty cycle correction circuit, comprising: an input node, wherein the voltage between said input node and ground is either at a high voltage level or a low voltage level; an output node, a first node, a second node, and a reference node; a first capacitor connected between said first node and said reference node; a second capacitor connected between said second node and said reference node; means for charging said first capacitor at a rate which varies inversely with the voltage drop from said second node to said reference node when the voltage between said input node and ground is said low voltage level; means for discharging said first capacitor at a rate which varies directly with the voltage drop from said second node to said reference node when the voltage between said input node and ground is said high voltage level; means for producing said low voltage level between said output node and ground when the voltage drop from said first node to said reference node is greater than a threshold voltage and said high voltage level between said output node and ground when the voltage drop from said first node to said reference node is less than said threshold voltage, wherein said means for producing said low voltage level between said output node and ground when the voltage drop from said first node to said reference node is greater than a threshold voltage and said high voltage level between said output node and ground when the voltage drop from said first node to said reference node is less than said threshold voltage comprises an inverter, wherein said inverter is used as a comparator, said inverter comprising a P channel metal oxide semiconductor field effect transistor and an N channel metal oxide semiconductor field effect transistor; means for charging said second capacitor when the voltage between said output node and ground is said low voltage level; and means for discharging said second capacitor when the voltage between said output node and ground is said high voltage level.
Claim 3
Dependent Claim
86 words
The clock duty cycle correction circuit of claim 1 , wherein said means for charging said first capacitor comprises a first current source and a first switch connected in series between a voltage supply node and said first node, wherein said first switch is closed and said first current source charges said first capacitor at a rate which varies inversely with the voltage drop from said second node to said reference node when the voltage between said input node and ground is said low voltage level.
Claim 4
Dependent Claim
35 words
The clock duty cycle correction circuit of claim 2 , wherein said first current source comprises a P channel metal oxide semiconductor field effect transistor having a gate which is connected to said second node.
Claim 5
Dependent Claim
34 words
The clock duty cycle correction circuit of claim 2 , wherein said first switch comprises a P channel metal oxide semiconductor field effect transistor having a gate which is connected to said input node.
Claim 6
Dependent Claim
85 words
The clock duty cycle correction circuit of claim 1 , wherein said means for discharging said first capacitor comprises a second current source and a second switch connected in series between said first node and said reference node, wherein said second switch is closed and said second current source discharges said first capacitor at a rate which varies directly with the voltage drop from said second node to said reference node when the voltage between said input node and ground is said high voltage level.
Claim 7
Dependent Claim
35 words
The clock duty cycle correction circuit of claim 5 , wherein said second current source comprises an N channel metal oxide semiconductor field effect transistor having a gate which is connected to said second node.
Claim 8
Dependent Claim
34 words
The clock duty cycle correction circuit of claim 5 , wherein said second switch comprises an N channel metal oxide semiconductor field effect transistor having a gate, which is connected to said input node.
Claim 9
Dependent Claim
60 words
The clock duty cycle correction circuit of claim 1 , wherein said means for charging said second capacitor further comprises a fifth current source and a fifth switch connected in series between a voltage supply node and said second node, wherein said fifth switch is closed when the voltage between said input node and ground is said low voltage level.
Claim 10
Dependent Claim
59 words
The clock duty cycle correction circuit of claim 1 , wherein said means for discharging said second capacitor further comprises a sixth current source and a sixth switch connected in series between said second node and said reference node, wherein said sixth switch is closed when the voltage between said input node and ground is said high voltage level.
Claim 11
Dependent Claim
318 words
A clock duty cycle correction circuit, comprising: an input node, wherein the voltage between said input node and ground is either at a high voltage level or a low voltage level; an output node, a first node, and a second node; a voltage supply node and a reference node; a first capacitor connected between said first node and said reference node; a second capacitor connected between said second node and said reference node; a first current source and a first switch connected in series between said voltage supply node and said first node, wherein said first switch is closed and said first current source charges said first capacitor when the voltage between said input node and ground is said low voltage level; a second current source and a second switch connected in series between said first node and said reference node, wherein said second switch is closed and said second current source discharges said first capacitor when the voltage between said input node and ground is said high voltage level; a comparator wherein said comparator comprises an inverter having an input, an output, a P channel metal oxide semiconductor field effect transistor, and an N channel metal oxide semiconductor field effect transistor, wherein said input is connected to said first node and said output is connected to said second node; a third current source and a third switch connected in series between said voltage supply node and said second node, wherein said third switch is closed and said third current source charges said second capacitor when the voltage between said output node and ground is said low voltage level; and a fourth current source and a fourth switch connected in series between said second node and said reference node, wherein said second switch is closed and said second current source discharges said second capacitor when the voltage between said output node and ground is said high voltage level.
Claim 12
Dependent Claim
318 words
A clock duty cycle correction circuit, comprising: an input node, wherein the voltage between said input node and ground is either at a high voltage level or a low voltage level; an output node, a first node, and a second node; a voltage supply node and a reference node; a first capacitor connected between said first node and said reference node; a second capacitor connected between said second node and said reference node; a first current source and a first switch connected in series between said voltage supply node and said first node, wherein said first switch is closed and said first current source charges said first capacitor when the voltage between said input node and ground is said low voltage level; a second current source and a second switch connected in series between said first node and said reference node, wherein said second switch is closed and said second current source discharges said first capacitor when the voltage between said input node and ground is said high voltage level; a comparator wherein said comparator comprises an inverter having an input, an output, a P channel metal oxide semiconductor field effect transistor, and an N channel metal oxide semiconductor field effect transistor, wherein said input is connected to said first node and said output is connected to said second node; a third current source and a third switch connected in series between said voltage supply node and said second node, wherein said third switch is closed and said third current source charges said second capacitor when the voltage between said output node and ground is said low voltage level; and a fourth current source and a fourth switch connected in series between said second node and said reference node, wherein said second switch is closed and said second current source discharges said second capacitor when the voltage between said output node and ground is said high voltage level.
Claim 13
Dependent Claim
35 words
The clock duty cycle correction circuit of claim 10 , wherein said first current source comprises a P channel metal oxide semiconductor field effect transistor having a gate which is connected to said second node.
Claim 14
Dependent Claim
34 words
The clock duty cycle correction circuit of claim 10 , wherein said first switch comprises a P channel metal oxide semiconductor field effect transistor having a gate which is connected to said input node.
Claim 15
Dependent Claim
34 words
The clock duty cycle correction circuit of claim 10 , wherein said third switch comprises a P channel metal oxide semiconductor field effect transistor having a gate which is connected to said output node.
Claim 16
Dependent Claim
35 words
The clock duty cycle correction circuit of claim 10 , wherein said second current source comprises an N channel metal oxide semiconductor field effect transistor having a gate which is connected to said second node.
Claim 17
Dependent Claim
34 words
The clock duty cycle correction circuit of claim 10 , wherein said second switch comprises an N channel metal oxide semiconductor field effect transistor having a gate which is connected to said input node.
Claim 18
Dependent Claim
34 words
The clock duty cycle correction circuit of claim 10 , wherein said fourth switch comprises an N channel metal oxide semiconductor field effect transistor having a gate which is connected to said output node.
Claim 19
Dependent Claim
62 words
The clock duty cycle correction circuit of claim 10 , further comprising a fifth current source and a fifth switch connected in series between said voltage supply node and said first node, and means for closing said fifth switch, whereby said fifth current source charges said first capacitor, when the voltage between said input node and ground is said low voltage level.
Claim 20
Dependent Claim
61 words
The clock duty cycle correction circuit of claim 10 , further comprising a sixth current source and a sixth switch connected in series between said first node and said reference node, and means for closing said sixth switch, whereby said sixth current source discharges said first capacitor, when the voltage between said input node and ground is said high voltage level.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2005-05-06 | 2005-11-05 | 2006-05-07 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2009-05-06 | 2009-11-05 | 2010-05-07 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2013-05-06 | 2013-11-05 | 2014-05-07 | $7700.00 | Window Closed / Lapsed |