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US6380765B1
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Double pass transistor logic with vertical gate transistors
Assignee: Micron Technology Inc
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Filing: 2000-08-29
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Granted: 2002-04-30
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Expires: 2020-08-29
Abstract
Abstract Systems and methods are provided for double pass transistor logic with vertical gate transistors. The vertical gate transistors have multiple vertical gates which are edge defined such that only a single transistor is required for multiple logic inputs. Thus, a minimal surface area is required for each logic input. In one embodiment, a novel integrated circuits described in the present invention includes a number of input lines for receiving input signals and at least one output line for providing output signals. One or more arrays of transistors are coupled between the number of input lines and the at least one output line. Each transistor includes source region and a drain region in a horizontal substrate. A depletion mode channel region separates the source and the drain regions. A number of vertical gates located above different portions of the depletion mode channel region. At least one of the vertical gates is located above a first portion of the depletion mode channel region and is separated from the channel region by a first thickness insulator material. Further at least one of the vertical gates is located above a second portion of the channel region and is separated from the channel region by a second thickness insulator material. The number of vertical gates each have a horizontal width which has sub-lithographic dimensions. In the invention, the number of vertical gates are independently coupled to a number of gate input lines. Thus, the number of vertical gates provide logic inputs such that a minimal area in each logic cell is used for each logic input. Other integrated circuits using the present invention are similarly provided.
Inventors
- 👤 Leonard Forbes
- 👤 Kie Y. Ahn
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 12:30
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/02; H03K19/173; H03K19/1733; H03K19/1737; H03K19/20; H03K19/21; H03K19/215; H10; H10D; H10D84/00; H10D84/01; H10D84/0123; H10D84/0126; H10D84/0135; H10D84/0144; H10D84/02; H10D84/03; H10D84/038
Claims Analysis
Total Claims: 118
Claim 1
Independent Claim
153 words
An integrated circuit, comprising: a number of input lines for receiving input signals; at least one output line for providing output signals; and one or more arrays of transistors coupled between the number of input lines and the at least one output line, wherein each transistor includes: a source region in a horizontal substrate; a drain region in the horizontal substrate; a depletion mode channel region separating the source and the drain regions; a number of vertical gates located above different portions of the depletion mode channel region; wherein at least one of the vertical gates is located above a first portion of the depletion mode channel region and is separated from the channel region by a first thickness insulator material; and wherein at least one of the vertical gates is located above a second portion of the channel region and is separated from the channel region by a second thickness insulator material.
Claim 2
Dependent Claim
153 words
An integrated circuit, comprising: a number of input lines for receiving input signals; at least one output line for providing output signals; and one or more arrays of transistors coupled between the number of input lines and the at least one output line, wherein each transistor includes: a source region in a horizontal substrate; a drain region in the horizontal substrate; a depletion mode channel region separating the source and the drain regions; a number of vertical gates located above different portions of the depletion mode channel region; wherein at least one of the vertical gates is located above a first portion of the depletion mode channel region and is separated from the channel region by a first thickness insulator material; and wherein at least one of the vertical gates is located above a second portion of the channel region and is separated from the channel region by a second thickness insulator material.
Claim 3
Dependent Claim
33 words
The integrated circuit of claim 1 , wherein at least one array of transistors includes an array of NMOS transistors and at least one array of transistors includes an array of PMOS transistors.
Claim 4
Dependent Claim
63 words
The integrated circuit of claim 1 , including at least one array of PMOS transistors, wherein each PMOS transistor is coupled to a different input line at the source region, wherein the drain regions for the array of PMOS transistors are coupled together to provide a single output, and wherein the number of vertical gates are coupled to a number of gate inputs.
Claim 5
Dependent Claim
45 words
The integrated circuit of claim 3 , wherein the number of vertical gates in each of the array of PMOS transistors are separated from the depletion mode channel by different combinations of the first insulator thickness material and second insulator thickness material in each transistor.
Claim 6
Dependent Claim
86 words
The integrated circuit of claim 3 , including at least one array of NMOS transistors, where each NMOS transistor is coupled to a different input line at the source region, wherein each input line couple to a source region of a PMOS transistor in the PMOS array is similarly coupled to one of the NMOS transistors in the NMOS array, and wherein the drain regions for the array of NMOS transistors are coupled together and coupled to the single output of the array of PMOS transistors.
Claim 7
Dependent Claim
41 words
The integrated circuit of claim 5 , wherein the number of vertical gates in the array of NMOS transistors are coupled to the identical number of gate inputs coupled to the number of vertical gates for the array of PMOS transistors.
Claim 8
Dependent Claim
19 words
The integrated circuit of claim 1 , wherein the number of input lines is four for each output line.
Claim 9
Dependent Claim
157 words
A double pass circuit, comprising: a number of input lines for receiving input signals; at least one output line for providing output signals; and one or more arrays of transistors coupled between the number of input lines and the at least one output line, wherein each transistor includes: a horizontal substrate, wherein the substrate includes a first source/drain region, a second source/drain region, and a depletion mode channel region separating the first and the second source/drain regions; a number of vertical gates located above different portions of the depletion mode channel region; wherein at least one of the vertical gates is located above a first portion of the depletion mode channel region and is separated from the channel region by a first thickness insulator material; and wherein at least one of the vertical gates is located above a second portion of the channel region and is separated from the channel region by a second thickness insulator material.
Claim 10
Dependent Claim
157 words
A double pass circuit, comprising: a number of input lines for receiving input signals; at least one output line for providing output signals; and one or more arrays of transistors coupled between the number of input lines and the at least one output line, wherein each transistor includes: a horizontal substrate, wherein the substrate includes a first source/drain region, a second source/drain region, and a depletion mode channel region separating the first and the second source/drain regions; a number of vertical gates located above different portions of the depletion mode channel region; wherein at least one of the vertical gates is located above a first portion of the depletion mode channel region and is separated from the channel region by a first thickness insulator material; and wherein at least one of the vertical gates is located above a second portion of the channel region and is separated from the channel region by a second thickness insulator material.
Claim 11
Dependent Claim
34 words
The double pass circuit of claim 8 , wherein at least one array of transistors includes an array of NMOS transistors and at least one array of transistors includes an array of PMOS transistors.
Claim 12
Dependent Claim
60 words
The double pass circuit of claim 9 , wherein the number of input lines couple to the first source/drain region in each transistor, and wherein each input line couples couples to a pair of first source/drain regions one of the pair being in the array of NMOS transistors and one of the pair being in the array of PMOS transistors.
Claim 13
Dependent Claim
24 words
The double pass circuit of claim 9 , wherein the second source/drain regions for the transistors are coupled together to provide a single output.
Claim 14
Dependent Claim
24 words
The double pass circuit of claim 9 , wherein the number of vertical gates are independently coupled to a number of gate input lines.
Claim 15
Dependent Claim
16 words
The double pass circuit of claim 8 , wherein the double pass circuit comprises a multiplexor.
Claim 16
Dependent Claim
24 words
The double pass circuit of claim 8 , wherein the number of vertical gates each have a horizontal width of approximately 100 nanometers (nm).
Claim 17
Dependent Claim
31 words
The double pass circuit of claim 8 , wherein the first thickness insulator material is approximately 33 Angstroms (Å), and wherein the second thickness insulator material is approximately 330 Angstroms (Å).
Claim 18
Dependent Claim
158 words
A multiplexor circuit, comprising: a number of input lines for receiving input signals; at least one output line for providing output signals; and one or more arrays of logic cells coupled between the number of input lines and the at least one output line, wherein each logic cell includes: a horizontal substrate, wherein the substrate includes a first source/drain region, a second source/drain region, and a depletion mode channel region separating the first and the second source/drain regions; a number of vertical gates located above different portions of the depletion mode channel region; wherein at least one of the vertical gates is located above a first portion of the depletion mode channel region and is separated from the channel region by a first thickness insulator material; and wherein at least one of the vertical gates is located above a second portion of the channel region and is separated from the channel region by a second thickness insulator material.
Claim 19
Dependent Claim
158 words
A multiplexor circuit, comprising: a number of input lines for receiving input signals; at least one output line for providing output signals; and one or more arrays of logic cells coupled between the number of input lines and the at least one output line, wherein each logic cell includes: a horizontal substrate, wherein the substrate includes a first source/drain region, a second source/drain region, and a depletion mode channel region separating the first and the second source/drain regions; a number of vertical gates located above different portions of the depletion mode channel region; wherein at least one of the vertical gates is located above a first portion of the depletion mode channel region and is separated from the channel region by a first thickness insulator material; and wherein at least one of the vertical gates is located above a second portion of the channel region and is separated from the channel region by a second thickness insulator material.
Claim 20
Dependent Claim
20 words
The multiplexor of claim 16 , wherein the number of vertical gates each have horizontal width which has sub-lithographic dimensions.
Claim 21
Dependent Claim
30 words
The multiplexor of claim 17 , wherein the number of vertical gates provide logic inputs such that a minimal area in each logic cell is used for each logic input.
Claim 22
Dependent Claim
34 words
The multiplexor of claim 16 , wherein at least one array of logic cells includes an array of NMOS transistors and at least one array of logic cells includes an array of PMOS transistors.
Claim 23
Dependent Claim
68 words
The multiplexor of claim 16 , wherein each vertical gate separated from a first portion of the depletion mode channel region by a first thickness insulator material controls conduction in the depletion mode channel, and wherein each vertical separated from a second portion of the depletion mode channel region by a second thickness insulator material has a minimal or no control over conduction in the depletion mode channel.
Claim 24
Dependent Claim
85 words
The multiplexor of claim 16 , wherein each array of logic cells includes a number of vertical gates separated from the channel region by a first thickness insulator material and a number of gates separated from the channel region by a second thickness insulator material, and wherein an arrangement of the gates separated by the first and the second thickness insulator material is different in each logic cell such that the number of vertical gates provide a number different logic inputs to each logic cell.
Claim 25
Dependent Claim
150 words
A complementary integrated circuit, comprising: a complementary pair of output lines; a number of input lines; and an array of transistors coupled between the complementary pair of output lines and the number of input lines, wherein each transistor in the array of transistors includes; a source region in a horizontal substrate; a drain region in the horizontal substrate; a depletion mode channel region separating the source and the drain regions; a number of vertical gates located above different portions of the depletion mode channel region; wherein at least one of the vertical gates is located above a first portion of the depletion mode channel region and is separated from the channel region by a first thickness insulator material; and wherein at least one of the vertical gates is located above a second portion of the channel region and is separated from the channel region by a second thickness insulator material.
Claim 26
Dependent Claim
150 words
A complementary integrated circuit, comprising: a complementary pair of output lines; a number of input lines; and an array of transistors coupled between the complementary pair of output lines and the number of input lines, wherein each transistor in the array of transistors includes; a source region in a horizontal substrate; a drain region in the horizontal substrate; a depletion mode channel region separating the source and the drain regions; a number of vertical gates located above different portions of the depletion mode channel region; wherein at least one of the vertical gates is located above a first portion of the depletion mode channel region and is separated from the channel region by a first thickness insulator material; and wherein at least one of the vertical gates is located above a second portion of the channel region and is separated from the channel region by a second thickness insulator material.
Claim 27
Dependent Claim
35 words
The complementary integrated circuit of claim 22 , wherein a number of the transistors in the array of transistors include PMOS transistors and a number of transistors in the array of transistors include NMOS transistors.
Claim 28
Dependent Claim
67 words
The complementary integrated circuit of claim 23 , wherein one of the complementary pair of output lines is coupled to a drain region for a first set of PMOS transistors and a first set of NMOS transistors, and wherein one of the complementary pair of output lines is coupled to a drain region for a second set of PMOS transistors and a second set of NMOS transistors.
Claim 29
Dependent Claim
27 words
The complementary integrated circuit of claim 22 , wherein the number of vertical gates in each transistor are coupled to a number of control variable input lines.
Claim 30
Dependent Claim
80 words
The complementary integrated circuit of claim 22 , wherein the at least one vertical gate separated from the channel region by a first thickness insulator material is able to control conduction within the depletion mode channel and serves as an active logic input, and wherein the at least one vertical gate separated from the channel region by a second thickness insulator material has a minimal or no ability to control conduction in the channel and serves as a passing line.
Claim 31
Dependent Claim
19 words
The complementary integrated circuit of claim 22 , wherein the first oxide thickness is less than 50 Angstroms (Å).
Claim 32
Dependent Claim
19 words
The complementary integrated circuit of claim 22 , wherein the second oxide thickness is less than 300 Angstroms (Å).
Claim 33
Dependent Claim
43 words
The complementary integrated circuit of claim 22 , wherein the depletion mode channel region separating the source and the drain regions is controlled by a potential range of less than 0.5 Volts applied to at least one of the number of vertical gates.
Claim 34
Dependent Claim
154 words
A complementary double pass circuit, comprising: a complementary pair of output lines; a number of input lines; and an array of transistors coupled between the complementary pair of output lines and the number of input lines, wherein each transistor in the array of transistors includes; a horizontal substrate, wherein the substrate includes a first source/drain region, a second source/drain region, and a depletion mode channel region separating the first and the second source/drain regions; a number of vertical gates located above different portions of the depletion mode channel region; wherein at least one of the vertical gates is located above a first portion of the depletion mode channel region and is separated from the channel region by a first thickness insulator material; and wherein at least one of the vertical gates is located above a second portion of the channel region and is separated from the channel region by a second thickness insulator material.
Claim 35
Dependent Claim
154 words
A complementary double pass circuit, comprising: a complementary pair of output lines; a number of input lines; and an array of transistors coupled between the complementary pair of output lines and the number of input lines, wherein each transistor in the array of transistors includes; a horizontal substrate, wherein the substrate includes a first source/drain region, a second source/drain region, and a depletion mode channel region separating the first and the second source/drain regions; a number of vertical gates located above different portions of the depletion mode channel region; wherein at least one of the vertical gates is located above a first portion of the depletion mode channel region and is separated from the channel region by a first thickness insulator material; and wherein at least one of the vertical gates is located above a second portion of the channel region and is separated from the channel region by a second thickness insulator material.
Claim 36
Dependent Claim
24 words
The complementary double pass circuit of claim 30 , wherein the array transistors includes a set of PMOS transistors and a set of NMOS.
Claim 37
Dependent Claim
31 words
The complementary double pass circuit of claim 30 , wherein the circuit further includes a number of control variable input lines coupled to the number of vertical gates in each transistor.
Claim 38
Dependent Claim
79 words
The complementary double pass circuit of claim 31 , wherein the at least one vertical gate separated from the depletion mode channel by a first thickness insulator material is able to control conduction in the depletion mode channel, and wherein the at least one vertical gate separated from the depletion mode channel by a first oxide thickness is coupled to a different one of the number of control variable input lines in different transistors in the array of transistors.
Claim 39
Dependent Claim
44 words
The complementary double pass circuit of claim 30 , wherein the first thickness insulator material includes an oxide having a thickness of less than 50 Angstroms, and wherein the second thickness insulator material includes an oxide having a thickness of less than 350 Angstroms.
Claim 40
Dependent Claim
40 words
The complementary double pass circuit of claim 30 , wherein the number of vertical gates each are sub-lithographic in dimension, and wherein the number of vertical gates provide multiple control variable inputs for the transistors in the array of transistors.
Claim 41
Dependent Claim
21 words
The complementary double pass circuit of claim 30 , wherein the number of input lines include a number of pass variables.
Claim 42
Dependent Claim
17 words
The complementary double pass circuit of claim 30 , wherein the circuit includes an exclusive OR/NOR circuit.
Claim 43
Dependent Claim
186 words
A complementary double pass circuit, comprising: a complementary pair of output lines; a number of input lines; and an array of logic cells including a first set of PMOS and NMOS transistor pairs coupled between one of the complementary pair of output lines and a first set of the number of input lines, and including a second set of PMOS and NMOS transistor pairs coupled between the other one of the complementary pair of output lines and a second set of the number of input lines, wherein each logic cell in the array of logic cells includes; a horizontal substrate, wherein the substrate includes a first source/drain region, a second source/drain region, and a depletion mode channel region separating the first and the second source/drain regions; a number of vertical gates located above different portions of the depletion mode channel region; wherein at least one of the vertical gates is separated from the depletion mode channel region by a first thickness insulator material; and wherein at least one of the vertical gates is separated from the depletion mode channel region by a second thickness insulator material.
Claim 44
Dependent Claim
186 words
A complementary double pass circuit, comprising: a complementary pair of output lines; a number of input lines; and an array of logic cells including a first set of PMOS and NMOS transistor pairs coupled between one of the complementary pair of output lines and a first set of the number of input lines, and including a second set of PMOS and NMOS transistor pairs coupled between the other one of the complementary pair of output lines and a second set of the number of input lines, wherein each logic cell in the array of logic cells includes; a horizontal substrate, wherein the substrate includes a first source/drain region, a second source/drain region, and a depletion mode channel region separating the first and the second source/drain regions; a number of vertical gates located above different portions of the depletion mode channel region; wherein at least one of the vertical gates is separated from the depletion mode channel region by a first thickness insulator material; and wherein at least one of the vertical gates is separated from the depletion mode channel region by a second thickness insulator material.
Claim 45
Dependent Claim
17 words
The complementary double pass circuit of claim 38 , wherein the circuit includes an exclusive OR/NOR circuit.
Claim 46
Dependent Claim
31 words
The complementary double pass circuit of claim 38 , wherein the circuit further includes a number of control variable input lines coupled to the number of vertical gates in each transistor.
Claim 47
Dependent Claim
47 words
The complementary double pass circuit of claim 40 , wherein the at least one vertical gate separated by a first thickness insulator material is arranged in each logic cell of the first set of PMOS and NMOS transistors to couple to a different control variable input line.
Claim 48
Dependent Claim
47 words
The complementary double pass circuit of claim 41 , wherein the at least one vertical gate separated by a first thickness insulator material is arranged in each logic cell of the second set of PMOS and NMOS transistors to couple to a different control variable input line.
Claim 49
Dependent Claim
90 words
The complementary double pass circuit of claim 38 , wherein in the at least one of the vertical gates separated from the depletion mode channel region by a first thickness insulator material serves as an active input capable of controlling conduction in the depletion mode channel, and wherein at least one of the vertical gates is separated from the depletion mode channel region by a second thickness insulator material serves as a passive gate which has a minimal or no effect on the conduction in the depletion mode channel region.
Claim 50
Dependent Claim
40 words
The complementary double pass circuit of claim 38 , wherein the number of vertical gates each are sub-lithographic in dimension, and wherein the number of vertical gates provide multiple control variable inputs for the transistors in the array of transistors.
Claim 51
Dependent Claim
172 words
An electronic system, comprising: a memory device; and a processor coupled to the memory device, wherein the processor includes an integrated circuit, comprising: a number of input lines for receiving input signals; at least one output line for providing output signals; and one or more arrays of transistors coupled between the number of input lines and the at least one output line, wherein each transistor includes: a source region in a horizontal substrate; a drain region in the horizontal substrate; a depletion mode channel region separating the source and the drain regions; a number of vertical gates located above different portions of the depletion mode channel region; wherein at least one of the vertical gates is located above a first portion of the depletion mode channel region and is separated from the channel region by a first thickness insulator material; and wherein at least one of the vertical gates is located above a second portion of the channel region and is separated from the channel region by a second thickness insulator material.
Claim 52
Dependent Claim
172 words
An electronic system, comprising: a memory device; and a processor coupled to the memory device, wherein the processor includes an integrated circuit, comprising: a number of input lines for receiving input signals; at least one output line for providing output signals; and one or more arrays of transistors coupled between the number of input lines and the at least one output line, wherein each transistor includes: a source region in a horizontal substrate; a drain region in the horizontal substrate; a depletion mode channel region separating the source and the drain regions; a number of vertical gates located above different portions of the depletion mode channel region; wherein at least one of the vertical gates is located above a first portion of the depletion mode channel region and is separated from the channel region by a first thickness insulator material; and wherein at least one of the vertical gates is located above a second portion of the channel region and is separated from the channel region by a second thickness insulator material.
Claim 53
Dependent Claim
33 words
The electronic system of claim 45 , wherein at least one array of transistors includes an array of NMOS transistors and at least one array of transistors includes an array of PMOS transistors.
Claim 54
Dependent Claim
57 words
The electronic system of claim 46 , wherein the number of input lines couple to the source region in each transistor, and wherein each input line couples couples to a pair of source regions one of the pair being in the array of NMOS transistors and one of the pair being in the array of PMOS transistors.
Claim 55
Dependent Claim
22 words
The electronic system of claim 45 , wherein the drain regions for the transistors are coupled together to provide a single output.
Claim 56
Dependent Claim
23 words
The electronic system of claim 45 , wherein the number of vertical gates are independently coupled to a number of gate input lines.
Claim 57
Dependent Claim
17 words
The electronic system of claim 45 , wherein the integrated circuit comprises a double pass multiplexor circuit.
Claim 58
Dependent Claim
23 words
The electronic system of claim 45 , wherein the number of vertical gates each have a horizontal width of approximately 100 nanometers (nm).
Claim 59
Dependent Claim
30 words
The electronic system of claim 45 , wherein the first thickness insulator material is approximately 33 Angstroms (Å), and wherein the second thickness insulator material is approximately 330 Angstroms (Å).
Claim 60
Dependent Claim
156 words
An electronic system, comprising: a memory device; and a processor coupled to the memory device, wherein the processor includes a multiplexor circuit, the multiplexor circuit comprising: a number of input lines for receiving input signals; at least one output line for providing output signals; and one or more arrays of logic cells coupled between the number of input lines and the at least one output line, wherein each logic cell includes: a horizontal substrate, wherein the substrate includes a first source/drain region, a second source/drain region, and a depletion mode channel region separating the first and the second source/drain regions; a number of vertical gates located above different portions of the depletion mode channel region; wherein at least one of the vertical gates is separated from the channel region by a first thickness insulator material; and wherein at least one of the vertical gates is separated from the channel region by a second thickness insulator material.
Claim 61
Dependent Claim
156 words
An electronic system, comprising: a memory device; and a processor coupled to the memory device, wherein the processor includes a multiplexor circuit, the multiplexor circuit comprising: a number of input lines for receiving input signals; at least one output line for providing output signals; and one or more arrays of logic cells coupled between the number of input lines and the at least one output line, wherein each logic cell includes: a horizontal substrate, wherein the substrate includes a first source/drain region, a second source/drain region, and a depletion mode channel region separating the first and the second source/drain regions; a number of vertical gates located above different portions of the depletion mode channel region; wherein at least one of the vertical gates is separated from the channel region by a first thickness insulator material; and wherein at least one of the vertical gates is separated from the channel region by a second thickness insulator material.
Claim 62
Dependent Claim
22 words
The electronic system of claim 53 , wherein the number of vertical gates each have a horizontal width which has sub-lithographic dimensions.
Claim 63
Dependent Claim
31 words
The electronic system of claim 53 , wherein the number of vertical gates provide logic inputs such that a minimal area in each logic cell is used for each logic input.
Claim 64
Dependent Claim
35 words
The electronic system of claim 53 , wherein at least one array of logic cells includes an array of NMOS transistors and at least one array of logic cells includes an array of PMOS transistors.
Claim 65
Dependent Claim
69 words
The electronic system of claim 53 , wherein each vertical gate separated from a first portion of the depletion mode channel region by a first thickness insulator material controls conduction in the depletion mode channel, and wherein each vertical separated from a second portion of the depletion mode channel region by a second thickness insulator material has a minimal or no control over conduction in the depletion mode channel.
Claim 66
Dependent Claim
86 words
The electronic system of claim 53 , wherein each array of logic cells includes a number of vertical gates separated from the channel region by a first thickness insulator material and a number of gates separated from the channel region by a second thickness insulator material, and wherein an arrangement of the gates separated by the first and the second thickness insulator material is different in each logic cell such that the number of vertical gates provide a number different logic inputs to each logic cell.
Claim 67
Dependent Claim
154 words
An electronic system, comprising: a memory device; and a processor coupled to the memory device, wherein the processor includes a complementary double pass circuit, the complementary double pass circuit comprising: a complementary pair of output lines; a number of input lines; and an array of transistors coupled between the complementary pair of output lines and the number of input lines, wherein each transistor in the array of transistors includes; a horizontal substrate, wherein the substrate includes a first source/drain region, a second source/drain region, and a depletion mode channel region separating the first and the second source/drain regions; a number of vertical gates located above different portions of the depletion mode channel region; wherein at least one of the vertical gates is separated from the channel region by a first thickness insulator material; and wherein at least one of the vertical gates is separated from the channel region by a second thickness insulator material.
Claim 68
Dependent Claim
154 words
An electronic system, comprising: a memory device; and a processor coupled to the memory device, wherein the processor includes a complementary double pass circuit, the complementary double pass circuit comprising: a complementary pair of output lines; a number of input lines; and an array of transistors coupled between the complementary pair of output lines and the number of input lines, wherein each transistor in the array of transistors includes; a horizontal substrate, wherein the substrate includes a first source/drain region, a second source/drain region, and a depletion mode channel region separating the first and the second source/drain regions; a number of vertical gates located above different portions of the depletion mode channel region; wherein at least one of the vertical gates is separated from the channel region by a first thickness insulator material; and wherein at least one of the vertical gates is separated from the channel region by a second thickness insulator material.
Claim 69
Dependent Claim
42 words
The electronic system of claim 59 , wherein the depletion mode channel region separating the source and the drain regions is controlled by a potential range of less than 0.5 Volts applied to at least one of the number of vertical gates.
Claim 70
Dependent Claim
23 words
The electronic system of claim 59 , wherein the array of transistors includes a set of PMOS transistors and a set of NMOS.
Claim 71
Dependent Claim
32 words
The electronic system of claim 59 , wherein the complementary double pass circuit further includes a number of control variable input lines coupled to the number of vertical gates in each transistor.
Claim 72
Dependent Claim
78 words
The electronic system of claim 62 , wherein the at least one vertical gate separated from the depletion mode channel by a first thickness insulator material is able to control conduction in the depletion mode channel, and wherein the at least one vertical gate separated from the depletion mode channel by the first thickness insulator material is coupled to a different one of the number of control variable input lines in different transistors in the array of transistors.
Claim 73
Dependent Claim
42 words
The electronic system of claim 59 , wherein the first thickness insulator material includes an oxide having a thickness of less than 50 Angstroms, and wherein the second thickness insulator material includes an oxide having a thickness of less than 350 Angstroms.
Claim 74
Dependent Claim
38 words
The electronic system of claim 59 , wherein the number of vertical gates each are sub-lithographic in dimension, and wherein the number of vertical gates provide multiple control variable inputs for the transistors in the array of transistors.
Claim 75
Dependent Claim
31 words
The electronic system of claim 59 , wherein the complementary double pass circuit includes an exclusive OR/NOR circuit, and wherein the number of input lines include a number of pass variables.
Claim 76
Dependent Claim
210 words
An electronic system, comprising: a memory device; and a processor coupled to the memory device, wherein the processor includes a complementary double pass circuit, the complementary double pass circuit comprising: a complementary pair of output lines; a number of input lines; and an array of logic cells including a first set of PMOS and NMOS transistor pairs coupled between one of the complementary pair of output lines and a first set of the number of input lines, and including a second set of PMOS and NMOS transistor pairs coupled between the other one of the complementary pair of output lines and a second set of the number of input lines, wherein each logic cell in the array of logic cells includes; a horizontal substrate, wherein the substrate includes a first source/drain region, a second source/drain region, and a depletion mode channel region separating the first and the second source/drain regions; a number of vertical gates located above different portions of the depletion mode channel region; wherein at least one of the vertical gates is separated from the depletion mode channel region by a first thickness insulator material; and wherein at least one of the vertical gates is separated from the depletion mode channel region by a second thickness insulator material.
Claim 77
Dependent Claim
210 words
An electronic system, comprising: a memory device; and a processor coupled to the memory device, wherein the processor includes a complementary double pass circuit, the complementary double pass circuit comprising: a complementary pair of output lines; a number of input lines; and an array of logic cells including a first set of PMOS and NMOS transistor pairs coupled between one of the complementary pair of output lines and a first set of the number of input lines, and including a second set of PMOS and NMOS transistor pairs coupled between the other one of the complementary pair of output lines and a second set of the number of input lines, wherein each logic cell in the array of logic cells includes; a horizontal substrate, wherein the substrate includes a first source/drain region, a second source/drain region, and a depletion mode channel region separating the first and the second source/drain regions; a number of vertical gates located above different portions of the depletion mode channel region; wherein at least one of the vertical gates is separated from the depletion mode channel region by a first thickness insulator material; and wherein at least one of the vertical gates is separated from the depletion mode channel region by a second thickness insulator material.
Claim 78
Dependent Claim
18 words
The electronic system of claim 67 , wherein the complementary double pass circuit includes an exclusive OR/NOR circuit.
Claim 79
Dependent Claim
33 words
The electronic system of claim 67 , wherein the complementary double pass circuit further includes a number of control variable input lines coupled to the number of vertical gates in each logic cell.
Claim 80
Dependent Claim
45 words
The electronic system of claim 69 , wherein the at least one vertical gate separated by a first thickness insulator material is arranged in each logic cell of the first set of PMOS and NMOS transistors to couple to a different control variable input line.
Claim 81
Dependent Claim
45 words
The electronic system of claim 70 , wherein the at least one vertical gate separated by a first thickness insulator material is arranged in each logic cell of the second set of PMOS and NMOS transistors to couple to a different control variable input line.
Claim 82
Dependent Claim
88 words
The electronic system of claim 69 , wherein the at least one of the vertical gates separated from the depletion mode channel region by a first thickness insulator material serves as an active input capable of controlling conduction in the depletion mode channel, and wherein the at least one of the vertical gates is separated from the depletion mode channel region by a second thickness insulator material serves as a passive gate which has a minimal or no effect on the conduction in the depletion mode channel region.
Claim 83
Dependent Claim
40 words
The electronic system of claim 69 , wherein the number of vertical gates each are sub-lithographic in dimension, and wherein the number of vertical gates provide multiple control variable inputs for the logic cells in the array of logic cells.
Claim 84
Independent Claim
158 words
A method for forming a multiplexor circuit, comprising: forming a number of input lines for receiving input signals; forming at least one output line for providing output signals; and forming one or more arrays of logic cells coupled between the number of input lines and the at least one output line, wherein forming each logic cell includes: forming a horizontal substrate, wherein the substrate includes a first source/drain region, a second source/drain region, and a depletion mode channel region separating the first and the second source/drain regions; forming a number of vertical gates located above different portions of the depletion mode channel region; wherein forming the number of vertical gates includes forming at least one of the vertical gates separated from the channel region by a first thickness insulator material; and wherein forming the number of vertical gates includes forming at least one of the vertical gates separated from the channel region by a second thickness insulator material.
Claim 85
Independent Claim
158 words
A method for forming a multiplexor circuit, comprising: forming a number of input lines for receiving input signals; forming at least one output line for providing output signals; and forming one or more arrays of logic cells coupled between the number of input lines and the at least one output line, wherein forming each logic cell includes: forming a horizontal substrate, wherein the substrate includes a first source/drain region, a second source/drain region, and a depletion mode channel region separating the first and the second source/drain regions; forming a number of vertical gates located above different portions of the depletion mode channel region; wherein forming the number of vertical gates includes forming at least one of the vertical gates separated from the channel region by a first thickness insulator material; and wherein forming the number of vertical gates includes forming at least one of the vertical gates separated from the channel region by a second thickness insulator material.
Claim 86
Dependent Claim
27 words
The method of claim 74 , wherein forming the number of vertical gates includes forming each vertical gate to have a horizontal width which has sub-lithographic dimensions.
Claim 87
Dependent Claim
28 words
The method of claim 74 , wherein forming the number of vertical gates includes forming each vertical gate to have a horizontal width of approximately 100 nanometers (nm).
Claim 88
Dependent Claim
41 words
The method of claim 74 , the method further including forming the first thickness insulator material to have a thickness of approximately 33 Angstroms (Å), and forming the second thickness insulator material to have a thickness of approximately 330 Angstroms (Å).
Claim 89
Dependent Claim
35 words
The method of claim 74 , the method further including forming the number of vertical gates to provide logic inputs such that a minimal area in each logic cell is used for each logic input.
Claim 90
Dependent Claim
41 words
The method of claim 74 , the method further including forming at least one array of logic cells to include an array of NMOS transistors and forming at least one array of logic cells to include an array of PMOS transistors.
Claim 91
Dependent Claim
86 words
The method of claim 74 , wherein forming at least one vertical gate separated by a first thickness insulator material from the depletion mode channel region includes forming the at least one vertical gate to control conduction in the depletion mode channel, and wherein forming the at least one vertical gate separated by a second thickness insulator material from the depletion mode channel region includes forming the at least one vertical gate to have a minimal or no control over conduction in the depletion mode channel.
Claim 92
Dependent Claim
92 words
The method of claim 74 , wherein forming at least one vertical gate separated by a first thickness insulator material from the depletion mode channel region and forming at least one vertical gate separated by a second thickness insulator material from the depletion mode channel region includes forming the number of vertical gates in an arrangement wherein the gates separated by the first and the second thickness insulator material are different in each logic cell such that the number of vertical gates provide a number different logic inputs to each logic cell.
Claim 93
Independent Claim
212 words
A method for forming a complementary double pass circuit, comprising: forming a complementary pair of output lines; forming a number of input lines; and forming an array of logic cells including forming a first set of PMOS and NMOS transistor pairs coupled between one of the complementary pair of output lines and a first set of the number of input lines, and including forming a second set of PMOS and NMOS transistor pairs coupled between the other one of the complementary pair of output lines and a second set of the number of input lines, wherein forming each logic cell in the array of logic cells includes; forming a horizontal substrate, wherein the substrate includes a first source/drain region, a second source/drain region, and a depletion mode channel region separating the first and the second source/drain regions; forming a number of vertical gates located above different portions of the depletion mode channel region; wherein forming a number of vertical gates includes forming at least one of the vertical gates separated from the depletion mode channel region by a first thickness insulator material; and wherein forming a number of vertical gates includes forming at least one of the vertical gates separated from the depletion mode channel region by a second thickness insulator material.
Claim 94
Independent Claim
212 words
A method for forming a complementary double pass circuit, comprising: forming a complementary pair of output lines; forming a number of input lines; and forming an array of logic cells including forming a first set of PMOS and NMOS transistor pairs coupled between one of the complementary pair of output lines and a first set of the number of input lines, and including forming a second set of PMOS and NMOS transistor pairs coupled between the other one of the complementary pair of output lines and a second set of the number of input lines, wherein forming each logic cell in the array of logic cells includes; forming a horizontal substrate, wherein the substrate includes a first source/drain region, a second source/drain region, and a depletion mode channel region separating the first and the second source/drain regions; forming a number of vertical gates located above different portions of the depletion mode channel region; wherein forming a number of vertical gates includes forming at least one of the vertical gates separated from the depletion mode channel region by a first thickness insulator material; and wherein forming a number of vertical gates includes forming at least one of the vertical gates separated from the depletion mode channel region by a second thickness insulator material.
Claim 95
Dependent Claim
22 words
The method of claim 82 , wherein forming the complementary double pass circuit includes forming an exclusive OR/NOR complementary double pass circuit.
Claim 96
Dependent Claim
32 words
The method of claim 82 , wherein forming the complementary double pass circuit includes forming a number of control variable input lines coupled to the number of vertical gates in each transistor.
Claim 97
Dependent Claim
50 words
The method of claim 82 , wherein forming at least one vertical gate separated by a first thickness insulator material includes forming the at least one vertical gate in each logic cell of the first set of PMOS and NMOS transistors to couple to a different control variable input line.
Claim 98
Dependent Claim
50 words
The method of claim 85 , wherein forming at least one vertical gate separated by a first thickness insulator material includes forming the at least one vertical gate in each logic cell of the second set of PMOS and NMOS transistors to couple to a different control variable input line.
Claim 99
Dependent Claim
90 words
The method of claim 85 , wherein forming at least one vertical gate separated by a first thickness insulator material includes forming the at least one vertical gate to serve as an active input capable of controlling conduction in the depletion mode channel, and wherein forming at least one of the vertical gate separated by a second thickness insulator material includes forming the at least one vertical gate to serve as a passive gate which has a minimal or no effect on the conduction in the depletion mode channel region.
Claim 100
Dependent Claim
58 words
The method of claim 85 , wherein forming the number of vertical gates includes forming each of the number of vertical gates to be sub-lithographic in dimension, and wherein forming the number of vertical gates includes forming the number of vertical gates to provide multiple control variable inputs for the logic cells in the array of logic cells.
Claim 101
Independent Claim
210 words
A method for operating a multiplexor circuit, comprising: providing a number of input signals on a number of input lines; providing a number of control variable signals on a number of gate lines, wherein the number of input lines couple to a source region in one or more arrays of logic cells coupled between the number of input lines and at least one output line, and wherein each logic cell includes: a horizontal substrate, wherein the substrate includes a first source/drain region, a second source/drain region, and a depletion mode channel region separating the first and the second source/drain regions; a number of vertical gates located above different portions of the depletion mode channel region, each vertical gate coupled to a gate line; wherein at least one of the vertical gates separated from the channel region by a first thickness insulator material; and wherein at least one of the vertical gates separated from the channel region by a second thickness insulator material; and wherein providing the number of control variable signals on the number of gate lines selectively controls conduction in the number of logic cells depending on whether the gate line couples to a vertical gate separated from the channel by a first or a second thickness insulator material.
Claim 102
Independent Claim
210 words
A method for operating a multiplexor circuit, comprising: providing a number of input signals on a number of input lines; providing a number of control variable signals on a number of gate lines, wherein the number of input lines couple to a source region in one or more arrays of logic cells coupled between the number of input lines and at least one output line, and wherein each logic cell includes: a horizontal substrate, wherein the substrate includes a first source/drain region, a second source/drain region, and a depletion mode channel region separating the first and the second source/drain regions; a number of vertical gates located above different portions of the depletion mode channel region, each vertical gate coupled to a gate line; wherein at least one of the vertical gates separated from the channel region by a first thickness insulator material; and wherein at least one of the vertical gates separated from the channel region by a second thickness insulator material; and wherein providing the number of control variable signals on the number of gate lines selectively controls conduction in the number of logic cells depending on whether the gate line couples to a vertical gate separated from the channel by a first or a second thickness insulator material.
Claim 103
Dependent Claim
31 words
The method of claim 89 , wherein providing the number of control variable signals on the number of gate lines includes providing a number of logic inputs to each logic cell.
Claim 104
Dependent Claim
38 words
The method of claim 89 , wherein providing a number of control variable signals includes providing the number of control variable signals to a number of vertical gates which have a horizontal width which are sub-lithographic in dimension.
Claim 105
Dependent Claim
41 words
The method of claim 89 , wherein providing a number of control variable signals includes providing the number of control variable signals to each logic cell such that a minimal area in each logic cell is used for each logic input.
Claim 106
Dependent Claim
35 words
The method of claim 89 , wherein providing a number of control variable signals includes providing the number of control variable signals to an array of NMOS transistors and to an array of PMOS transistors.
Claim 107
Dependent Claim
115 words
The method of claim 89 , wherein providing a number of control variable signals includes providing the number of control variable signals to at least one vertical gate separated by a first thickness insulator material from the depletion mode channel region such that the at least one vertical gate to controls conduction in the depletion mode channel, and wherein providing a number of control variable signals includes providing the number of control variable signals to at least one vertical gate separated by a second thickness insulator material from the depletion mode channel region such that the at least one vertical gate to has a minimal or no control over conduction in the depletion mode channel.
Claim 108
Dependent Claim
29 words
The method of claim 89 , wherein the method further includes outputting an output signals from the multiplexor based on a sensed conduction in the arrays of logic cells.
Claim 109
Independent Claim
264 words
A method for operating a complementary double pass circuit, comprising: providing a number of input signals on a number of input lines; providing a complementary pair of output signals on a complementary pair of output lines; providing a number of control variable signals on a number of gate lines, wherein the complementary pair of output lines couple to a drain region in one or more arrays of transistors, wherein one of the complementary pair of output lines couples to a drain region for a first set of PMOS and NMOS transistors, and wherein one of the complementary pair of output lines couples to a drain region for a second set of PMOS and NMOS transistors, wherein each transistor in the array of transistors includes: a horizontal substrate, wherein the substrate includes a first source/drain region, a second source/drain region, and a depletion mode channel region separating the first and the second source/drain regions; a number of vertical gates located above different portions of the depletion mode channel region, each vertical gate coupled to a gate line; wherein at least one of the vertical gates separated from the channel region by a first thickness insulator material; and wherein at least one of the vertical gates separated from the channel region by a second thickness insulator material; and wherein providing the number of control variable signals on the number of gate lines selectively controls conduction in the number of transistors depending on whether the gate line couples to a vertical gate separated from the depletion mode channel by a first or a second thickness insulator material.
Claim 110
Independent Claim
264 words
A method for operating a complementary double pass circuit, comprising: providing a number of input signals on a number of input lines; providing a complementary pair of output signals on a complementary pair of output lines; providing a number of control variable signals on a number of gate lines, wherein the complementary pair of output lines couple to a drain region in one or more arrays of transistors, wherein one of the complementary pair of output lines couples to a drain region for a first set of PMOS and NMOS transistors, and wherein one of the complementary pair of output lines couples to a drain region for a second set of PMOS and NMOS transistors, wherein each transistor in the array of transistors includes: a horizontal substrate, wherein the substrate includes a first source/drain region, a second source/drain region, and a depletion mode channel region separating the first and the second source/drain regions; a number of vertical gates located above different portions of the depletion mode channel region, each vertical gate coupled to a gate line; wherein at least one of the vertical gates separated from the channel region by a first thickness insulator material; and wherein at least one of the vertical gates separated from the channel region by a second thickness insulator material; and wherein providing the number of control variable signals on the number of gate lines selectively controls conduction in the number of transistors depending on whether the gate line couples to a vertical gate separated from the depletion mode channel by a first or a second thickness insulator material.
Claim 111
Dependent Claim
30 words
The method of claim 96 , wherein providing the number of control variable signals on the number of gate lines includes providing a number of logic inputs to each transistor.
Claim 112
Dependent Claim
54 words
The method of claim 96 , wherein operating the complementary double pass circuit further includes inputting a number of pass variables on a number of input lines and outputting a complementary pair of output signals on the complementary pair of output lines based on conduction through the depletion mode channels in array of transistors.
Claim 113
Dependent Claim
55 words
The method of claim 96 , wherein providing a number of control variable signals on the number of gate lines includes applying a negative potential of approximately −0.6 Volts to at least one of the number of vertical gates such that the at least one vertical gate turns off conduction in the depletion mode channel.
Claim 114
Dependent Claim
35 words
The method of claim 96 , wherein providing a number of control variable signals on the number of gate lines includes applying a potential to a number of vertical gates which serve as passing lines.
Claim 115
Dependent Claim
31 words
The method of claim 96 , wherein providing a number of control variable signals on the number of gate lines includes independently applying potential values to the number of vertical gates.
Claim 116
Dependent Claim
57 words
The method of claim 96 , wherein providing a number of control variable signals on the number of gate lines includes using at least one of the number of vertical gates in any transistor as a passing line includes and using at least one of the number of vertical gates in any transistor as an active input.
Claim 117
Dependent Claim
46 words
The method of claim 96 , wherein providing a number of control variable signals on the number of gate lines includes providing a number of control variable signals to a number of edge defined vertical gates which have a horizontal width which is sub-lithographic in dimension.
Claim 118
Dependent Claim
42 words
The method of claim 96 , wherein providing a number of control variable signals includes providing an number of logic inputs to each transistor such that less than one MOSFET is used for each logic input to the complementary double pass circuit.
References Cited (Backward Citations)
US6124729A
Cited
US6222788B1
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