Patent US6378018B1 successfully refreshed from Google Patents.
US6378018B1
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Memory device and system including a low power interface
Assignee: Rambus Inc
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Filing: 1998-10-09
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Granted: 2002-04-23
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Expires: 2018-10-09
Abstract
Abstract A memory system includes an interconnect structure with a high speed channel and a low speed channel. A memory device with interface circuitry is coupled to the interconnect structure. The interface circuitry includes a high power interface for coupling to the high speed channel and a low power interface for coupling to the low speed channel. The memory device is operative in a low power mode and a high power mode. A memory controller is coupled to the high speed channel and the low speed channel of the interconnect structure. The memory controller is configured to transmit control information over the low speed channel to set the power mode of the memory device. The memory device is operative in a low power mode during which high power receiver circuits are turned off. The memory device is also operative in a nap mode during which an internal clock compensation circuit is left on to preserve phase information. The memory system may include multiple memory devices coupled to a daisy chained lead of the interconnect structure. The memory controller may be configured to apply control information to the interconnect structure as an encoded device identification word. The memory devices may each include a decoder for interpreting the encoded device identification word. The memory controller may be configured to apply a memory device selection signal to the interconnect structure to selectively enable the memory devices.
Inventors
- 👤 Ely K. Tsern
- 👤 Thomas J. Holman
- 👤 Richard M. Barth
- 👤 Andrew V. Anderson
- 👤 Paul G. Davis
- 👤 Craig E. Hampel
- 👤 Donald C. Stark
- 👤 Abhijit M. Abhyankar
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 22:17
CPC Classifications
G; G06; G06F; G06F13/00; G06F13/38; G06F13/42; G06F13/4204; G06F13/4234; G06F13/4243; G06F13/14; G06F13/16; G06F13/1668; G06F13/1694; Y; Y02; Y02D; Y02D10/00
Claims Analysis
Total Claims: 34
Claim 1
Independent Claim
114 words
A memory system, comprising: an interconnect structure having a high speed channel and a low speed channel; a memory device, said memory device having interface circuitry coupled to said interconnect structure, said interface circuitry including a high power interface for coupling to said high speed channel and a low power interface for coupling to said low speed channel, said memory device being operative in a low power mode and a high power mode; and a memory controller coupled to said high speed channel and said low speed channel of said interconnect structure, said memory controller configured to transmit control information over said low speed channel to set the power mode of said memory device.
Claim 2
Dependent Claim
114 words
A memory system, comprising: an interconnect structure having a high speed channel and a low speed channel; a memory device, said memory device having interface circuitry coupled to said interconnect structure, said interface circuitry including a high power interface for coupling to said high speed channel and a low power interface for coupling to said low speed channel, said memory device being operative in a low power mode and a high power mode; and a memory controller coupled to said high speed channel and said low speed channel of said interconnect structure, said memory controller configured to transmit control information over said low speed channel to set the power mode of said memory device.
Claim 3
Dependent Claim
30 words
The memory system of claim 1 wherein said memory device is operative in a low power mode during which high power receiver circuits of said interface circuitry are turned off.
Claim 4
Dependent Claim
13 words
The memory system of claim 1 wherein said interconnect structure is a bus.
Claim 5
Dependent Claim
29 words
The memory system of claim 1 wherein said memory controller is configured to apply said control information to said interconnect structure on both edges of a control clock signal.
Claim 6
Dependent Claim
43 words
The memory system of claim 1 wherein there are a plurality of memory devices and wherein said memory controller is configured to apply control information to said interconnect structure that is simultaneously received by each memory device of said plurality of memory devices.
Claim 7
Dependent Claim
73 words
The memory system of claim 1 wherein there are a plurality of memory devices and wherein said memory controller is configured to apply control information to said interconnect structure as an encoded device identification word, said memory system further comprising a decoder connected to said interconnect structure to process said encoded device identification word and generate a decoded control signal that is applied to selected memory devices of said plurality of memory devices.
Claim 8
Dependent Claim
45 words
The memory system of claim 1 wherein said memory controller is configured to apply control information to said interconnect structure that is processed by said memory device high speed interface to transition said memory device from said high power mode to said low power mode.
Claim 9
Dependent Claim
31 words
The memory system of claim 1 wherein said memory device includes a programmable storage bit whose value determines whether said memory device is responsive to a parallel identification device selection signal.
Claim 10
Dependent Claim
37 words
The memory system of claim 1 wherein said memory controller is configured to apply control information to said low speed channel to transition said selected memory device from said high power mode to said low power mode.
Claim 11
Dependent Claim
106 words
The memory system of claim 1 , wherein there are a plurality of memory devices; and wherein the interface circuitry in each of said memory devices includes a power mode condition bit which is set whenever a respective one of said memory devices enters a low power mode and is reset whenever a memory core operation occurs within the respective memory device, so that when the interface circuitry of each of the memory devices receives a conditional nap entry command following a nap exit command, only selected memory devices of said plurality of memory devices having the condition bit set return to said low power mode.
Claim 12
Dependent Claim
34 words
The memory system of claim 1 wherein said memory device is operable in a nap mode during which an internal clock compensation circuit of said interface circuitry is left on to preserve phase information.
Claim 13
Dependent Claim
36 words
The memory system of claim 11 wherein said internal clock compensation circuit includes a delay locked loop circuit coupled to said interconnect structure, wherein the delay locked loop circuit preserves state information during said nap mode.
Claim 14
Dependent Claim
33 words
The memory system of claim 1 wherein there are a plurality of memory devices, said interconnect structure including a daisy chained lead connected between each memory device of said plurality of memory devices.
Claim 15
Dependent Claim
34 words
The memory system of claim 13 wherein said plurality of memory devices include bidirectional daisy chain circuits to support bidirectional communication between any one of said plurality of memory devices and said memory controller.
Claim 16
Dependent Claim
50 words
The memory system of claim 1 wherein said memory controller is configured to apply control information to said interconnect structure as an encoded device identification word, said memory system further comprising a plurality of memory devices wherein each memory device includes a decoder for interpreting said encoded device identification word.
Claim 17
Dependent Claim
16 words
The memory system of claim 15 wherein said decoder is connected to said high speed channel.
Claim 18
Dependent Claim
35 words
The memory system of claim 15 wherein said memory controller is configured to apply a memory device selection signal to said interconnect structure to enable selected memory devices to interpret said encoded device identification word.
Claim 19
Dependent Claim
34 words
The memory system of claim 1 wherein said memory device includes a sequenced turn-on control circuit coupled to said low power channel to transition from said low power mode to said high power mode.
Claim 20
Dependent Claim
17 words
The memory system of claim 18 wherein said sequenced turn-on control circuit is a one-shot timing circuit.
Claim 21
Dependent Claim
32 words
The memory system of claim 18 wherein said sequenced turn-on control circuit includes an internal counter which counts clock cycles from a low power clock signal received via said low power channel.
Claim 22
Dependent Claim
27 words
The memory system of claim 20 wherein said sequenced turn-on control circuit includes programmable registers coupled to the internal counter to store count values for timing events.
Claim 23
Dependent Claim
84 words
A memory device for coupling to an interconnect structure that includes a high speed channel and a low speed channel, comprising: a memory core for storing data; and interface circuitry coupled to said memory core, said interface circuitry including a high power interface for coupling with said high speed channel and a low power interface for coupling with said low speed channel, said interface circuitry configured to receive control information from said low speed channel to set a power mode of said memory device.
Claim 24
Dependent Claim
84 words
A memory device for coupling to an interconnect structure that includes a high speed channel and a low speed channel, comprising: a memory core for storing data; and interface circuitry coupled to said memory core, said interface circuitry including a high power interface for coupling with said high speed channel and a low power interface for coupling with said low speed channel, said interface circuitry configured to receive control information from said low speed channel to set a power mode of said memory device.
Claim 25
Dependent Claim
30 words
The memory device of claim 22 wherein said memory device is operable in a low power mode during which high power receiver circuits of said interface circuitry are turned off.
Claim 26
Dependent Claim
34 words
The memory device of claim 22 wherein said memory device is operable in a nap mode during which an internal clock compensation circuit of said interface circuitry is left on to preserve phase information.
Claim 27
Dependent Claim
34 words
The memory system of claim 22 wherein said interface circuitry includes a delay locked loop circuit coupled to said memory core, wherein the delay locked loop circuit preserves state information during a nap mode.
Claim 28
Dependent Claim
28 words
The memory device of claim 22 further comprising a programmable storage bit whose value determines whether said memory device is responsive to a parallel identification device selection signal.
Claim 29
Dependent Claim
28 words
The memory device of claim 22 wherein said interface circuitry includes a bidirectional serial port to support bidirectional communication over a single pin with an adjacent memory device.
Claim 30
Dependent Claim
20 words
The memory device of claim 22 wherein said interface circuitry includes a decoder for interpreting an encoded device identification word.
Claim 31
Dependent Claim
34 words
The memory device of claim 22 wherein said memory device includes a sequenced turn-on control circuit coupled to the low speed channel to transition from said low power mode to said high power mode.
Claim 32
Dependent Claim
17 words
The memory device of claim 29 wherein said sequenced turn-on control circuit is a one-shot timing circuit.
Claim 33
Dependent Claim
32 words
The memory device of claim 29 wherein said sequenced turn-on control circuit includes an internal counter which counts clock cycles from a low power clock signal received via the low speed channel.
Claim 34
Dependent Claim
27 words
The memory device of claim 31 wherein said sequenced turn-on control circuit includes programmable registers coupled to the internal counter to store count values for timing events.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2005-04-22 | 2005-10-22 | 2006-04-23 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2009-04-22 | 2009-10-22 | 2010-04-23 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2013-04-22 | 2013-10-22 | 2014-04-23 | $7700.00 | Window Closed / Lapsed |