Programmable memory controller

Claim 2

A synchronous dynamic random access memory controller comprising: a high speed interface having an input buffer with input entry buffers for receiving transactions, said input buffer having a valid bit for each input entry buffer, said input entry buffers storing transactions received from a high speed bus; and a low speed interface for retrieving transactions from said input buffer, said low speed interface including a memory sequencer that uses said valid bit for each of said input entry buffers to synchronize said high speed interface with respect to said low speed interface, wherein said high speed interface has an input buffer state machine that, after storing one of said transactions in one of said input entry buffers, sets a corresponding input entry buffer valid bit, an output buffer for outputting data to said high speed bus, said output buffer having output entry buffers with output data beat buffers, each output data beat buffer of each output entry buffer having an output data beat buffer valid bit, and an output buffer state machine that, after outputting data in response to a read transaction stored in one of said output entry buffers, resets a corresponding output data beat buffer valid bit, and said memory sequencer initially sets said input entry buffer valid bits and said output data beat buffer valid bits.

Claim 3

The synchronous dynamic random access memory controller of claim 1 , wherein said memory sequencer, in response to a write transaction stored in one of said input entry buffers, resets a corresponding input entry buffer valid bit after storing data beats associated with said write transaction in a synchronous dynamic random access memory, and in response to a read transaction stored in one of said input entry buffers, stores a data beat from said synchronous dynamic random access memory in one of said output data beat buffers and sets a corresponding output data beat buffer valid bit.

Claim 4

A synchronous dynamic random access memory controller comprising: a high speed interface having an input buffer with input entry buffers for receiving transactions, said input buffer having a valid bit for each input entry buffer, said input entry buffers storing transactions received from a high speed bus; and a low speed interface for retrieving transactions from said input buffer, said low speed interface including a memory sequencer that uses said valid bit for each of said input entry buffers to synchronize said high speed interface with respect to said low speed interface, wherein said input entry buffers have a plurality of input data beat buffers for receiving data beats from said high speed bus, and said high speed interface further comprises: a command queue state machine having an input entry pointer buffer that stores an input entry pointer, and having an input beat pointer buffer that stores an input beat pointer, said input entry pointer pointing to one of said input entry buffers of said input buffer, said input beat pointer pointing to one of said input data beat buffers.

Claim 5

A synchronous dynamic random access memory controller comprising: a high speed interface having an input buffer with input entry buffers for receiving transactions, said input buffer having a valid bit for each input entry buffer, said input entry buffers storing transactions received from a high speed bus; and a low speed interface for retrieving transactions from said input buffer, said low speed interface including a memory sequencer that uses said valid bit for each of said input entry buffers to synchronize said high speed interface with respect to said low speed interface, wherein said input entry buffers have a plurality of input data beat buffers for receiving data beats from said high speed bus, and said high speed interface further comprises: a command queue state machine having an input entry pointer buffer that stores an input entry pointer, and having an input beat pointer buffer that stores an input beat pointer, said input entry pointer pointing to one of said input entry buffers of said input buffer, said input beat pointer pointing to one of said input data beat buffers.

Claim 6

A synchronous dynamic random access memory controller comprising: a high speed interface having an input buffer with input entry buffers for receiving transactions, said input buffer having a valid bit for each input entry buffer, said input entry buffers storing transactions received from a high speed bus; and a low speed interface for retrieving transactions from said input buffer, said low speed interface including a memory sequencer that uses said valid bit for each of said input entry buffers to synchronize said high speed interface with respect to said low speed interface, wherein said high speed interface further comprises: an output buffer for outputting data beats to said high speed bus, said output buffer having a plurality of output entry buffers having a plurality of output data beat buffers, and a data return state machine having an output entry pointer buffer that stores an output entry pointer, and also having an output beat pointer buffer that stores an output beat pointer, said output entry pointer pointing to a particular output entry buffer of said output buffer, said output beat pointer pointing to a particular output data beat buffer of said particular output entry buffer, such that data stored in said particular output data beat buffer will be output to said high speed bus.

Claim 7

A synchronous dynamic random access memory controller comprising: a high speed interface having an input buffer with input entry buffers for receiving transactions, said input buffer having a valid bit for each input entry buffer, said input entry buffers storing transactions received from a high speed bus; and a low speed interface for retrieving transactions from said input buffer, said low speed interface including a memory sequencer that uses said valid bit for each of said input entry buffers to synchronize said high speed interface with respect to said low speed interface, wherein said high speed interface further comprises: an output buffer for outputting data beats to said high speed bus, said output buffer having a plurality of output entry buffers having a plurality of output data beat buffers, and a data return state machine having an output entry pointer buffer that stores an output entry pointer, and also having an output beat pointer buffer that stores an output beat pointer, said output entry pointer pointing to a particular output entry buffer of said output buffer, said output beat pointer pointing to a particular output data beat buffer of said particular output entry buffer, such that data stored in said particular output data beat buffer will be output to said high speed bus.

Claim 8

A synchronous dynamic random access memory controller comprising: a high speed interface having an input buffer with input entry buffers for receiving transactions, said input buffer having a valid bit for each input entry buffer, said input entry buffers storing transactions received from a high speed bus; and a low speed interface for retrieving transactions from said input buffer, said low speed interface including a memory sequencer that uses said valid bit for each of said input entry buffers to synchronize said high speed interface with respect to said low speed interface wherein said memory sequencer further comprises: a master entry pointer buffer that stores a master entry pointer for accessing said input entry buffers of said input buffer, and a master beat pointer buffer that stores a master beat pointer for accessing said input data beat buffers of said input buffer, said memory sequencer retrieving transactions stored in said input entry buffers using said master entry pointer and said master beat pointer.

Claim 9

A synchronous dynamic random access memory controller comprising: a high speed interface having an input buffer with input entry buffers for receiving transactions, said input buffer having a valid bit for each input entry buffer, said input entry buffers storing transactions received from a high speed bus; and a low speed interface for retrieving transactions from said input buffer, said low speed interface including a memory sequencer that uses said valid bit for each of said input entry buffers to synchronize said high speed interface with respect to said low speed interface wherein said memory sequencer further comprises: a master entry pointer buffer that stores a master entry pointer for accessing said input entry buffers of said input buffer, and a master beat pointer buffer that stores a master beat pointer for accessing said input data beat buffers of said input buffer, said memory sequencer retrieving transactions stored in said input entry buffers using said master entry pointer and said master beat pointer.

Claim 10

A synchronous dynamic random access memory controller comprising: a high speed interface having an input buffer with input entry buffers for receiving transactions, said input buffer having a valid bit for each input entry buffer, said input entry buffers storing transactions received from a high speed bus; and a low speed interface for retrieving transactions from said input buffer, said low speed interface including a memory sequencer that uses said valid bit for each of said input entry buffers to synchronize said high speed interface with respect to said low speed interface, wherein: said high speed interface receives a first transaction and a second transaction for accessing a synchronous dynamic random access memory (SDRAM); and said low speed interface retrieves said first transaction, maps said first transaction to a first set of SDRAM signals, retrieves said second transaction, maps said second transaction to a second set of SDRAM signals, outputs said first set of SDRAM signals, and outputs at least a portion of said second set of SDRAM signals before said SDRAM access for said first set of SDRAM signals is complete.

Claim 11

A synchronous dynamic random access memory controller comprising: a high speed interface having an input buffer with input entry buffers for receiving transactions, said input buffer having a valid bit for each input entry buffer, said input entry buffers storing transactions received from a high speed bus; and a low speed interface for retrieving transactions from said input buffer, said low speed interface including a memory sequencer that uses said valid bit for each of said input entry buffers to synchronize said high speed interface with respect to said low speed interface, wherein: said high speed interface receives a first transaction and a second transaction for accessing a synchronous dynamic random access memory (SDRAM); and said low speed interface retrieves said first transaction, maps said first transaction to a first set of SDRAM signals, retrieves said second transaction, maps said second transaction to a second set of SDRAM signals, outputs said first set of SDRAM signals, and outputs at least a portion of said second set of SDRAM signals before said SDRAM access for said first set of SDRAM signals is complete.

Claim 12

A synchronous dynamic random access memory system comprising: a plurality of SDRAMS, wherein each SDRAM has internal memory banks and each internal memory bank has an address, and said plurality of SDRAMs are organized into ranks, each rank having a rank address; a high speed interface having an input buffer with input entry buffers for receiving transactions, said input buffer having a valid bit for each input entry buffer, said input entry buffers storing transactions received from a high speed bus; and a low speed interface for retrieving transactions from said input buffer, said low speed interface including a memory sequencer that uses said valid bit for each of said input entry buffers to synchronize said high speed interface with respect to said low speed interface; and a plurality of state machines in said low speed interface for controlling a sequence of outputting first and second sets of SDRAM signals to an SDRAM of said plurality of SDRAMS, each state machine being dedicated to a different internal memory bank of said SDRAM, said first set of SDRAM signals for accessing a first SDRAM internal memory bank in a first rank address, said second set of SDRAM signals for accessing a first SDRAM internal memory bank in a second rank address.

Claim 13

A synchronous dynamic random access memory system comprising: a plurality of SDRAMS, wherein each SDRAM has internal memory banks and each internal memory bank has an address, and said plurality of SDRAMs are organized into ranks, each rank having a rank address; a high speed interface having an input buffer with input entry buffers for receiving transactions, said input buffer having a valid bit for each input entry buffer, said input entry buffers storing transactions received from a high speed bus; and a low speed interface for retrieving transactions from said input buffer, said low speed interface including a memory sequencer that uses said valid bit for each of said input entry buffers to synchronize said high speed interface with respect to said low speed interface; and a plurality of state machines in said low speed interface for controlling a sequence of outputting first and second sets of SDRAM signals to an SDRAM of said plurality of SDRAMS, each state machine being dedicated to a different internal memory bank of said SDRAM, said first set of SDRAM signals for accessing a first SDRAM internal memory bank in a first rank address, said second set of SDRAM signals for accessing a first SDRAM internal memory bank in a second rank address.

Claim 14

A computer system comprising: an execution unit; a bus interface unit coupled to said execution unit; a synchronous dynamic random access memory (SDRAM); a synchronous dynamic random access memory controller, connected to said SDRAM and said bus interface unit, said synchronous dynamic random access memory controller including: a high speed interface having an input buffer with input entry buffers for receiving transactions, said input buffer having an input entry buffer valid bit for each input entry buffer, said input entry buffers for storing transactions received from a high speed bus; and a low speed interface for retrieving transactions from said input buffer, said low speed interface including a memory sequencer that uses said input entry buffer valid bit for each of said input entry buffers to synchronize said high speed interface with respect to said low speed interface; wherein: said high speed interface has an input buffer state machine that, after storing one of said transactions in one said input entry buffers, sets a corresponding input entry buffer valid bit, an output buffer for outputting data to said high speed bus, said output buffer having output entry buffers with output data beat buffers, each output data beat buffer of each output entry buffer having an output data beat buffer valid bit, and an output buffer state machine that, after outputting data in response to a read transaction stored in one of said output entry buffers, resets a corresponding output data beat buffer valid bit, and said memory sequencer is configured to initialize said input entry buffer valid bits, and said output data beat buffer valid bits.

Claim 15

A computer system comprising: an execution unit; a bus interface unit coupled to said execution unit; a synchronous dynamic random access memory (SDRAM); a synchronous dynamic random access memory controller, connected to said SDRAM and said bus interface unit, said synchronous dynamic random access memory controller including: a high speed interface having an input buffer with input entry buffers for receiving transactions, said input buffer having an input entry buffer valid bit for each input entry buffer, said input entry buffers for storing transactions received from a high speed bus; and a low speed interface for retrieving transactions from said input buffer, said low speed interface including a memory sequencer that uses said input entry buffer valid bit for each of said input entry buffers to synchronize said high speed interface with respect to said low speed interface; wherein: said high speed interface has an input buffer state machine that, after storing one of said transactions in one said input entry buffers, sets a corresponding input entry buffer valid bit, an output buffer for outputting data to said high speed bus, said output buffer having output entry buffers with output data beat buffers, each output data beat buffer of each output entry buffer having an output data beat buffer valid bit, and an output buffer state machine that, after outputting data in response to a read transaction stored in one of said output entry buffers, resets a corresponding output data beat buffer valid bit, and said memory sequencer is configured to initialize said input entry buffer valid bits, and said output data beat buffer valid bits.

Claim 16

The computer system of claim 8 , wherein said memory sequencer, in response to a write transaction stored in one of said input entry buffers, resets a corresponding input entry buffer valid bit after storing data beats associated with said write transaction in said synchronous dynamic random access memory, and in response to a read transaction stored in one of said input entry buffers, stores a data beat from said synchronous dynamic random access memory in one of said output data beat buffers and sets a corresponding output data beat buffer valid bit.

Claim 17

A computer system comprising: an execution unit; a bus interface unit coupled to said execution unit; a synchronous dynamic random access memory (SDRAM), a synchronous dynamic random access memory controller, connected to said SDRAM and said bus interface unit, said synchronous dynamic random access memory controller including: a high speed interface having an input buffer with input entry buffers for receiving transactions, said input buffer having an input entry buffer valid bit for each input entry buffer, said input entry buffers for storing transactions received from a high speed bus; and a low speed interface for retrieving transactions from said input buffer, said low speed interface including a memory sequencer that uses said input entry buffer valid bit for each of said input entry buffers to synchronize said high speed interface with respect to said low speed interface; wherein: said input entry buffers have a plurality of input data beat buffers for receiving data beats from said high speed bus, and said high speed interface further comprises: a command queue state machine having an input entry pointer buffer that stores an input entry pointer, and having an input beat pointer buffer that stores an input beat pointer, said input entry pointer pointing to one of said input entry buffers of said input buffer, said input beat pointer pointing to one of said input data beat buffers.

Claim 18

A computer system comprising: an execution unit; a bus interface unit coupled to said execution unit; a synchronous dynamic random access memory (SDRAM), a synchronous dynamic random access memory controller, connected to said SDRAM and said bus interface unit, said synchronous dynamic random access memory controller including: a high speed interface having an input buffer with input entry buffers for receiving transactions, said input buffer having an input entry buffer valid bit for each input entry buffer, said input entry buffers for storing transactions received from a high speed bus; and a low speed interface for retrieving transactions from said input buffer, said low speed interface including a memory sequencer that uses said input entry buffer valid bit for each of said input entry buffers to synchronize said high speed interface with respect to said low speed interface; wherein: said input entry buffers have a plurality of input data beat buffers for receiving data beats from said high speed bus, and said high speed interface further comprises: a command queue state machine having an input entry pointer buffer that stores an input entry pointer, and having an input beat pointer buffer that stores an input beat pointer, said input entry pointer pointing to one of said input entry buffers of said input buffer, said input beat pointer pointing to one of said input data beat buffers.

Claim 19

A computer system comprising: an execution unit; a bus interface unit coupled to said execution unit; a synchronous dynamic random access memory (SDRAM); a synchronous dynamic random access memory controller, connected to said SDRAM and said bus interface unit, said synchronous dynamic random access memory controller including: a high speed interface having an input buffer with input entry buffers for receiving transactions, said input buffer having an input entry buffer valid bit for each input entry buffer, said input entry buffers for storing transactions received from a high speed bus; and a low speed interface for retrieving transactions from said input buffer, said low speed interface including a memory sequencer that uses said input entry buffer valid bit for each of said input entry buffers to synchronize said high speed interface with respect to said low speed interface; wherein said high speed interface further comprises: an output buffer for outputting data beats to said high speed bus, said output buffer having a plurality of output entry buffers each having a plurality of output data beat buffers, and a data return state machine having an output entry pointer buffer that stores an output entry pointer, and also having an output beat pointer buffer that stores an output beat pointer, said output entry pointer pointing to a particular output entry buffer of said output buffer, said output beat pointer pointing to a particular output data beat buffer of said particular output entry buffer, such that data stored in said particular output data beat buffer will be output to said high speed bus.

Claim 20

A computer system comprising: an execution unit; a bus interface unit coupled to said execution unit; a synchronous dynamic random access memory (SDRAM); a synchronous dynamic random access memory controller, connected to said SDRAM and said bus interface unit, said synchronous dynamic random access memory controller including: a high speed interface having an input buffer with input entry buffers for receiving transactions, said input buffer having an input entry buffer valid bit for each input entry buffer, said input entry buffers for storing transactions received from a high speed bus; and a low speed interface for retrieving transactions from said input buffer, said low speed interface including a memory sequencer that uses said input entry buffer valid bit for each of said input entry buffers to synchronize said high speed interface with respect to said low speed interface; wherein said high speed interface further comprises: an output buffer for outputting data beats to said high speed bus, said output buffer having a plurality of output entry buffers each having a plurality of output data beat buffers, and a data return state machine having an output entry pointer buffer that stores an output entry pointer, and also having an output beat pointer buffer that stores an output beat pointer, said output entry pointer pointing to a particular output entry buffer of said output buffer, said output beat pointer pointing to a particular output data beat buffer of said particular output entry buffer, such that data stored in said particular output data beat buffer will be output to said high speed bus.

Claim 21

A computer system comprising: an execution unit; a bus interface unit coupled to said execution unit; a synchronous dynamic random access memory (SDRAM); a synchronous dynamic random access memory controller, connected to said SDRAM and said bus interface unit, said synchronous dynamic random access memory controller including: a high speed interface having an input buffer with input entry buffers for receiving transactions, said input buffer having an input entry buffer valid bit for each input entry buffer, said input entry buffers for storing transactions received from a high speed bus; and a low speed interface for retrieving transactions from said input buffer, said low speed interface including a memory sequencer that uses said input entry buffer valid bit for each of said input entry buffers to synchronize said high speed interface with respect to said low speed interface; wherein said a memory sequencer further comprises: a current entry pointer buffer that stores a current entry pointer for accessing said input entry buffers of said input buffer, and a current beat pointer buffer that stores a current beat pointer for accessing said input data beat buffers of said input buffer, said memory sequencer retrieving transactions stored in said input entry buffers using said current pointer and said current beat pointer.

Claim 22

A computer system comprising: an execution unit; a bus interface unit coupled to said execution unit; a synchronous dynamic random access memory (SDRAM); a synchronous dynamic random access memory controller, connected to said SDRAM and said bus interface unit, said synchronous dynamic random access memory controller including: a high speed interface having an input buffer with input entry buffers for receiving transactions, said input buffer having an input entry buffer valid bit for each input entry buffer, said input entry buffers for storing transactions received from a high speed bus; and a low speed interface for retrieving transactions from said input buffer, said low speed interface including a memory sequencer that uses said input entry buffer valid bit for each of said input entry buffers to synchronize said high speed interface with respect to said low speed interface; wherein said a memory sequencer further comprises: a current entry pointer buffer that stores a current entry pointer for accessing said input entry buffers of said input buffer, and a current beat pointer buffer that stores a current beat pointer for accessing said input data beat buffers of said input buffer, said memory sequencer retrieving transactions stored in said input entry buffers using said current pointer and said current beat pointer.

Claim 23

A computer system comprising: an execution unit; a bus interface unit coupled to said execution unit; a synchronous dynamic random access memory (SDRAM); a synchronous dynamic random access memory controller, connected to said SDRAM and said bus interface unit, said synchronous dynamic random access memory controller including: a high speed interface having an input buffer with input entry buffers for receiving transactions, said input buffer having an input entry buffer valid bit for each input entry buffer, said input entry buffers for storing transactions received from a high speed bus; and a low speed interface for retrieving transactions from said input buffer, said low speed interface including a memory sequencer that uses said input entry buffer valid bit for each of said input entry buffers to synchronize said high speed interface with respect to said low speed interface; wherein said high speed interface receives a first transaction and a second transaction for accessing said synchronous dynamic random access memory (SDRAM); and said low speed interface retrieves said first transaction, maps said first transaction to a first set of SDRAM signals, retrieves said second transaction, maps said second transaction to a second set of SDRAM signals, outputs said first set of SDRAM signals, and outputs at least a portion of said second set of SDRAM signals before said SDRAM access for said first set of SDRAM signals is complete.

Claim 24

A computer system comprising: an execution unit; a bus interface unit coupled to said execution unit; a synchronous dynamic random access memory (SDRAM); a synchronous dynamic random access memory controller, connected to said SDRAM and said bus interface unit, said synchronous dynamic random access memory controller including: a high speed interface having an input buffer with input entry buffers for receiving transactions, said input buffer having an input entry buffer valid bit for each input entry buffer, said input entry buffers for storing transactions received from a high speed bus; and a low speed interface for retrieving transactions from said input buffer, said low speed interface including a memory sequencer that uses said input entry buffer valid bit for each of said input entry buffers to synchronize said high speed interface with respect to said low speed interface; wherein said high speed interface receives a first transaction and a second transaction for accessing said synchronous dynamic random access memory (SDRAM); and said low speed interface retrieves said first transaction, maps said first transaction to a first set of SDRAM signals, retrieves said second transaction, maps said second transaction to a second set of SDRAM signals, outputs said first set of SDRAM signals, and outputs at least a portion of said second set of SDRAM signals before said SDRAM access for said first set of SDRAM signals is complete.