US5548735A
Expired / Lapsed
US
⏱️ 0.0 years remaining
System and method for asynchronously processing store instructions to I/O space
Assignee: International Business Machines Corp
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Filing: 1993-09-15
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Granted: 1996-08-20
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Expires: 2013-09-15
Abstract
Abstract A system and method for asynchronously managing the issuance of program I/O store instructions from a high speed central processor to a multiplicity of relatively lower speed I/O adapter devices. An interface between the central processor and the I/O adapter devices includes a program I/O store queue, a state machine, and a token pool related in count to the concurrent processing capabilities of I/O controllers. The interface queue includes information for uniquely identifying program I/O store instructions by adapter device destination and user application program to manage error recovery. As preferably implemented, the interface system and method also distinctly manages program I/O instructions requiring synchronous execution, such as program I/O load instructions.
Inventors
- 👤 Wen-Tzer T. Chen
- 👤 Steven M. Thurber
- 👤 Gary Y. Tsao
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 14:12
CPC Classifications
G; G06; G06F; G06F13/00; G06F13/10; G06F13/12; G06F13/124; G06F13/126; G06F13/14; G06F13/36
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
113 words
An interface system for coupling a main processor to multiple bus controllers, said interface system comprising: an I/O queue for receiving and storing multiple I/O storage instructions received from said main processor; means for releasing said main processor for resumption of execution of program instructions in response to storage of an I/O storage instruction within said I/O queue; means for uniquely relating each I/O storage instruction within said I/O queue to a particular bus controller utilizing a token pool; and means for initiating asychronous issuance of an I/O storage instruction from said I/O queue to said particular bus controller wherein said main processor is not delayed awaiting completion of said I/O storage instruction.
Claim 2
Dependent Claim
113 words
An interface system for coupling a main processor to multiple bus controllers, said interface system comprising: an I/O queue for receiving and storing multiple I/O storage instructions received from said main processor; means for releasing said main processor for resumption of execution of program instructions in response to storage of an I/O storage instruction within said I/O queue; means for uniquely relating each I/O storage instruction within said I/O queue to a particular bus controller utilizing a token pool; and means for initiating asychronous issuance of an I/O storage instruction from said I/O queue to said particular bus controller wherein said main processor is not delayed awaiting completion of said I/O storage instruction.
Claim 3
Dependent Claim
45 words
The interface system according to claim 1, wherein said means for initiating asynchronous of an I/O storage instruction from said I/O queue to said bus controller comprises a state machine responsive to a net of received and issued I/O storage instructions within said I/O queue.
Claim 4
Dependent Claim
16 words
The interface system according to claim 1, further including means for recovering from an I/O interrupt.
Claim 5
Independent Claim
96 words
A method of operating an interface between a main processor and multiple bus controllers, said method comprising the data processing system implemented steps of: receiving and storing multiple I/O storage instructions from said main processor within an I/O queue; releasing said main processor for resumption of execution of program instructions in response to each storage of an I/O storage instruction with said I/O queue; thereafter, initiating asynchronous issuance of an I/O storage instruction from said I/O queue to said particular bus controller wherein said main processor is not delayed awaiting completion of said I/O storage instruction.
Claim 6
Independent Claim
96 words
A method of operating an interface between a main processor and multiple bus controllers, said method comprising the data processing system implemented steps of: receiving and storing multiple I/O storage instructions from said main processor within an I/O queue; releasing said main processor for resumption of execution of program instructions in response to each storage of an I/O storage instruction with said I/O queue; thereafter, initiating asynchronous issuance of an I/O storage instruction from said I/O queue to said particular bus controller wherein said main processor is not delayed awaiting completion of said I/O storage instruction.
Claim 7
Dependent Claim
77 words
The method of operating an interface between a main processor and a bus controller according to claim 4, wherein said step of initiating asynchronous issuance of an I/O storage instruction from said I/O queue to said particular bus controller further comprises the step of initiating asynchronous issuance of an I/O storage instruction from said I/O queue to said particular bus controller in response to a net of received and issued I/O storage instructions within said I/O queue.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-08-20 | 2000-02-19 | 2000-08-20 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-08-20 | 2004-02-19 | 2004-08-20 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-08-20 | 2008-02-19 | 2008-08-20 | $7700.00 | Window Closed / Lapsed |