Double pass band amplifier circuit and a radio frequency reception head

Claim 2

An amplifier circuit including: at least one first input amplifier; at least one second amplifier cascode connected with the at least one first amplifier; and at least one reactive impedance circuit coupled in series with the at least one second amplifier, including two impedances respectively exhibiting a maximum value for a first and a second frequency, to form a double-band amplifier circuit.

Claim 3

The amplifier circuit of claim 1 , wherein said impedances are associated in series and are sized to each exhibit a maximum value and a high quality factor on one of the two operating frequencies of the circuit.

Claim 4

The amplifier circuit of claim 1 , wherein each impedance is formed by an inductance in parallel with a capacitor.

Claim 5

The amplifier circuit of claim 3 , wherein the respective ratios between the inductance and the capacitor of each impedance range between 3,000 and 4,500.

Claim 6

The amplifier circuit of claim 3 , wherein the inductances and capacitors of the impedances are sized so that the square root of the ratio between the inductance and the capacitance of the first impedance is greater than 10 10 times the value of the inductance of the second impedance, and that the square root of the ratio between the impedance and the capacitance of the second impedance is greater than 0.5*10 10 times the value of the inductance of the first impedance.

Claim 7

The amplifier circuit of claim 1 , comprising two identical branches in parallel, each formed of a cascode assembly of a first and of a second amplifier, in series with a reactive impedance circuit.

Claim 8

The amplifier circuit of claim 6 , comprising differential inputs the respective impedances of which are sized to obtain a wide band matching covering the two operating frequency bands of the amplifier.

Claim 9

A receiver circuit, comprising: a radio frequency signal reception head configured to operate on two bands of different frequencies, the reception head comprising: at least one first amplifier having an input terminal; at least one second amplifier connected in cascode with the at least one first amplifier; and at least one reactive impedance circuit coupled in series with the second amplifier, the at least one reactive impedance circuit including a first impedance exhibiting a maximum value for a first frequency and a second impedance exhibiting a maximum value for a second frequency, the first and second impedances forming a double-band amplifier.

Claim 10

A receiver circuit, comprising: a radio frequency signal reception head configured to operate on two bands of different frequencies, the reception head comprising: at least one first amplifier having an input terminal; at least one second amplifier connected in cascode with the at least one first amplifier; and at least one reactive impedance circuit coupled in series with the second amplifier, the at least one reactive impedance circuit including a first impedance exhibiting a maximum value for a first frequency and a second impedance exhibiting a maximum value for a second frequency, the first and second impedances forming a double-band amplifier.

Claim 11

The circuit of claim 8 , wherein each of the first and second impedances is formed by an inductance coupled in parallel with a capacitor.

Claim 12

The circuit of claim 9 , further comprising a ratio between the inductance and the capacitor of each impedance, the ratio configured to be in the range of 3,000 to 4,500.

Claim 13

The circuit of claim 9 , further comprising a ratio between the inductance and the capacitor of each impedance, and wherein the inductances and capacitors of the impedances are sized to have the square root of the ratio between the inductance and the capacitance of the first impedance greater than 10 10 times the value of the inductance of the second impedance, and the square root of the ratio between the impedance and the capacitance of the second impedance is greater than 0.5*10 10 times the value of the inductance of the first impedance.

Claim 14

The circuit of claim 8 , comprising two identical branches in parallel, each formed of a cascode assembly of the first amplifier and the second amplifier in series with the reactive impedance circuit.

Claim 15

The circuit of claim 12 , wherein the input terminal of the first amplifier of each branch together comprise differential inputs.

Claim 16

The circuit of claim 13 , wherein the impedances are sized to obtain a frequency band covering the first and second frequencies of the first and second amplifiers.

Claim 17

An amplifier circuit, comprising: first and second parallel branches, each branch comprising: a first transistor having a control terminal coupled to a reference terminal, a first terminal coupled to a supply voltage, and a second terminal; a second transistor having a control terminal coupled to an input, a first terminal coupled to the second terminal of the first transistor, and a second terminal coupled to a current source; and a reactive impedance circuit coupled in series between the supply voltage and the first terminal of the first transistor, the reactive impedance circuit comprising series coupled first and second capacitors connected in parallel with series coupled first and second inductances.

Claim 18

An amplifier circuit, comprising: first and second parallel branches, each branch comprising: a first transistor having a control terminal coupled to a reference terminal, a first terminal coupled to a supply voltage, and a second terminal; a second transistor having a control terminal coupled to an input, a first terminal coupled to the second terminal of the first transistor, and a second terminal coupled to a current source; and a reactive impedance circuit coupled in series between the supply voltage and the first terminal of the first transistor, the reactive impedance circuit comprising series coupled first and second capacitors connected in parallel with series coupled first and second inductances.

Claim 19

The circuit of claim 15 , comprising a node between the reactive impedance circuit and the first transistor of each parallel branch, each node forming an output, and the control terminals of the second transistors comprise differential inputs.

Claim 20

The circuit of claim 16 , further comprising an inductance coupled between the current source and the second terminal of the second transistor in each parallel branch.

Claim 21

The circuit of claim 17 , wherein the current source comprises a single current source coupled to the first and second parallel branches.

Claim 22

The circuit of claim 18 , further comprising a connection formed between the first and second capacitors and the first and, second inductors in each of the first and second parallel branches.