Patent US6366135B1 successfully refreshed from Google Patents.
US6366135B1
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US
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Data frequency detector
Assignee: RPX Corp
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Filing: 1999-12-23
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Granted: 2002-04-02
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Expires: 2019-12-23
Abstract
Abstract A circuit comprising a first circuit and a state machine. The first circuit may be configured to generate a plurality of state inputs in response to (i) a first clock signal, (ii) a second clock signal delayed from the first clock signal, and (iii) a data signal. The state machine may be configured to generate a pump up signal and a pump down signal in response to (i) said data signal and (ii) a plurality of quadrants defined by a number of possible combinations of the state inputs. The state machine may be further configured to transition between any of the quadrants.
Inventors
- 👤 Kamal Dalmia
- 👤 Anil Agarwal
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 22:17
CPC Classifications
H; H03; H03D; H03D13/00; H03D13/003; H03D13/004
Claims Analysis
Total Claims: 20
Claim 1
Independent Claim
107 words
A circuit comprising: a first circuit configured to generate a plurality of state inputs in response to (i) a first clock signal, (ii) a second clock signal delayed from said first clock signal, and (iii) a data signal; a state machine configured to generate a pump up signal and a pump down signal in response to (i) said data signal and (ii) signals in a plurality of quadrants defined by a number of possible combinations of said state inputs, wherein said state machine is further configured to transition between any of the quadrants by transitioning to a next state in response to one or more previous states.
Claim 2
Dependent Claim
107 words
A circuit comprising: a first circuit configured to generate a plurality of state inputs in response to (i) a first clock signal, (ii) a second clock signal delayed from said first clock signal, and (iii) a data signal; a state machine configured to generate a pump up signal and a pump down signal in response to (i) said data signal and (ii) signals in a plurality of quadrants defined by a number of possible combinations of said state inputs, wherein said state machine is further configured to transition between any of the quadrants by transitioning to a next state in response to one or more previous states.
Claim 3
Dependent Claim
23 words
The circuit according to claim 1 , wherein said second clock signal is delayed 90 degrees with respect to said first clock signal.
Claim 4
Dependent Claim
28 words
The circuit according to claim 1 , wherein said state machine is further configured to transition to a next state in response to one or more previous states.
Claim 5
Dependent Claim
19 words
The circuit according to claim 3 , wherein said one or more previous states comprise transitions between consecutive quadrants.
Claim 6
Dependent Claim
26 words
The circuit according to claim 1 , wherein said state machine is further configured to check between a pair of quadrants of said plurality of quadrants.
Claim 7
Dependent Claim
15 words
The circuit according to claim 5 , wherein said pair of quadrants comprise consecutive quadrants.
Claim 8
Dependent Claim
24 words
The circuit according to claim 5 , wherein said state machine is further configured to check between said pair of quadrants to reduce jitter.
Claim 9
Dependent Claim
25 words
The circuit according to claim 7 , wherein said state machine is further configured to determine if a next state depends on a previous state.
Claim 10
Dependent Claim
101 words
A circuit comprising: means for generating a plurality of state inputs in response to (i) a first clock signal, (ii) a second clock signal delayed from said first clock signal, and (iii) a data signal; means for generating a pump up signal and a pump down signal in response to (i) said data signal and (ii) signals in a plurality of quadrants defined by a number of possible combinations of said state inputs, wherein said state machine is further configured to transition between any of the quadrants by transitioning to a next state in response to one or more previous states.
Claim 11
Dependent Claim
101 words
A circuit comprising: means for generating a plurality of state inputs in response to (i) a first clock signal, (ii) a second clock signal delayed from said first clock signal, and (iii) a data signal; means for generating a pump up signal and a pump down signal in response to (i) said data signal and (ii) signals in a plurality of quadrants defined by a number of possible combinations of said state inputs, wherein said state machine is further configured to transition between any of the quadrants by transitioning to a next state in response to one or more previous states.
Claim 12
Independent Claim
109 words
A method configured to detect one or more frequencies comprising the steps of: (A) generating a plurality of state inputs in response to (i) a first clock signal, (ii) a second clock signal delayed from said first clock signal, and (iii) a data signal; (B) generating a pump up signal and a pump down signal in response to (i) said data signal and (ii) signals in a plurality of quadrants defined by a number of possible combinations of said state inputs, wherein said state machine is further configured to transition between any of the quadrants by transitioning to a next state in response to one or more previous states.
Claim 13
Independent Claim
109 words
A method configured to detect one or more frequencies comprising the steps of: (A) generating a plurality of state inputs in response to (i) a first clock signal, (ii) a second clock signal delayed from said first clock signal, and (iii) a data signal; (B) generating a pump up signal and a pump down signal in response to (i) said data signal and (ii) signals in a plurality of quadrants defined by a number of possible combinations of said state inputs, wherein said state machine is further configured to transition between any of the quadrants by transitioning to a next state in response to one or more previous states.
Claim 14
Dependent Claim
19 words
The method according to claim 10 , wherein said one or more previous states comprise transitions between consecutive quadrants.
Claim 15
Dependent Claim
27 words
The method according to claim 10 , further comprising the following step: (C) repeating said step (A) between a pair of quadrants of said plurality of quadrants.
Claim 16
Dependent Claim
15 words
The method according to claim 12 , wherein said pair of quadrants comprise consecutive quadrants.
Claim 17
Dependent Claim
19 words
The method according to claim 12 , wherein step (C) further comprises checking said step (A) to reduce jitter.
Claim 18
Dependent Claim
22 words
The method according to claim 14 , wherein step (C) further comprises determining if a next state depends on a previous state.
Claim 19
Dependent Claim
119 words
A circuit comprising: a first circuit configured to generate a plurality of state inputs in response to (i) a first clock signal, (ii) a second clock signal delayed from said first clock signal, and (iii) a data signal; a state machine configured to generate a pump up signal and a pump down signal in response to (i) said data signal and (ii) signals in a plurality of quadrants defined by a number of possible combinations of said state inputs, wherein said state machine is further configured to transition between any of the quadrants and check between a pair of quadrants of said plurality of quadrants by transitioning to a next state in response to one or more previous states.
Claim 20
Dependent Claim
119 words
A circuit comprising: a first circuit configured to generate a plurality of state inputs in response to (i) a first clock signal, (ii) a second clock signal delayed from said first clock signal, and (iii) a data signal; a state machine configured to generate a pump up signal and a pump down signal in response to (i) said data signal and (ii) signals in a plurality of quadrants defined by a number of possible combinations of said state inputs, wherein said state machine is further configured to transition between any of the quadrants and check between a pair of quadrants of said plurality of quadrants by transitioning to a next state in response to one or more previous states.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2005-04-01 | 2005-10-01 | 2006-04-02 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2009-04-01 | 2009-10-01 | 2010-04-02 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2013-04-01 | 2013-10-01 | 2014-04-02 | $7700.00 | Window Closed / Lapsed |