Interconnection resources for programmable logic integrated circuit devices

Claim 2

A programmable logic integrated circuit device comprising: a plurality of regions of programmable logic disposed on the device in a two-dimensional array of intersecting rows and columns of said regions, each of said regions being programmable to perform any of a plurality of logic functions on a plurality of logic region input signals applied to the logic region to produce at least one logic region output signal; a plurality of interconnection conductors associated with each of the rows and configured to convey signals to, from, and/or between the logic regions in the associated row; and at least one programmable logic connector respectively associated with each of the interconnection conductors and configured to programmably select any of a plurality of PLC input signals applied to the programmable logic connector for application to the interconnection conductor associated with that programmable logic connector, at least one of the PLC input signals applied to each programmable logic connector being the logic region output signal of a logic region in the row associated with the interconnection conductor that the programmable logic connector applies a signal to, and at least one other of the PLC input signals applied to each programmable logic connector being the logic region output signal of a logic region in another row which is applied to the programmable logic connector substantially directly from the logic region in the other row.

Claim 3

The device defined in claim 1 wherein the other row is adjacent to the row associated with the interconnection conductor that the programmable logic connector applies a signal to.

Claim 4

A programmable logic integrated circuit device comprising: a plurality of regions of programmable logic disposed on the device in a two-dimensional array of intersecting rows and columns of said regions, each of said regions being programmable to perform any of a plurality of logic functions on a plurality of logic region input signals applied to the logic region to produce at least one logic region output signal; a plurality of interconnection conductors associated with each of the rows and configured to convey signals to, from, and/or between the logic regions in the associated row; at least one programmable logic connector respectively associated with each of the interconnection conductors and configured to programmably select any of a plurality of PLC input signals applied to the programmable logic connector for application to the interconnection conductor associated with that programmable logic connector, at least one of the PLC input signals applied to each programmable logic connector being the logic region output signal of a logic region in the row associated with the interconnection conductor that the programmable logic connector applies a signal to, and at least one other of the PLC input signals applied to each programmable logic connector being the logic region output signal of a logic region in another row which is applied to the programmable logic connector substantially directly from the logic region in the other row; and wherein a third one of the PLC input signals applied to each programmable logic connector is the logic region output signal of a logic region in a third row which is applied to the programmable logic connector substantially directly from the logic region in the third row.

Claim 5

A programmable logic integrated circuit device comprising: a plurality of regions of programmable logic disposed on the device in a two-dimensional array of intersecting rows and columns of said regions, each of said regions being programmable to perform any of a plurality of logic functions on a plurality of logic region input signals applied to the logic region to produce at least one logic region output signal; a plurality of interconnection conductors associated with each of the rows and configured to convey signals to, from, and/or between the logic regions in the associated row; at least one programmable logic connector respectively associated with each of the interconnection conductors and configured to programmably select any of a plurality of PLC input signals applied to the programmable logic connector for application to the interconnection conductor associated with that programmable logic connector, at least one of the PLC input signals applied to each programmable logic connector being the logic region output signal of a logic region in the row associated with the interconnection conductor that the programmable logic connector applies a signal to, and at least one other of the PLC input signals applied to each programmable logic connector being the logic region output signal of a logic region in another row which is applied to the programmable logic connector substantially directly from the logic region in the other row; and wherein a third one of the PLC input signals applied to each programmable logic connector is the logic region output signal of a logic region in a third row which is applied to the programmable logic connector substantially directly from the logic region in the third row.

Claim 6

The device defined in claim 3 wherein the other row and the third row are both adjacent to, but on opposite sides of, the row associated with the interconnection conductor that the programmable logic connector applies a signal to.

Claim 7

A programmable logic integrated circuit device comprising: a plurality of regions of programmable logic disposed on the device in a two-dimensional array of intersecting rows and columns of said regions, each of said regions being programmable to perform any of a plurality of logic functions on a plurality of logic region input signals applied to the logic region to produce at least one logic region output signal; a plurality of interconnection conductors associated with each of the rows and configured to convey signals to, from, and/or between the logic regions in the associated row; at least one programmable logic connector respectively associated with each of the interconnection conductors and configured to programmably select any of a plurality of PLC input signals applied to the programmable logic connector for application to the interconnection conductor associated with that programmable logic connector, at least one of the PLC input signals applied to each programmable logic connector being the logic region output signal of a logic region in the row associated with the interconnection conductor that the programmable logic connector applies a signal to, and at least one other of the PLC input signals applied to each programmable logic connector being the logic region output signal of a logic region in another row which is applied to the programmable logic connector substantially directly from the logic region in the other row; and a driver associated with each programmable logic connector and configured to strengthen the signal that the programmable logic connector applies to the associated interconnection conductor.

Claim 8

A programmable logic integrated circuit device comprising: a plurality of regions of programmable logic disposed on the device in a two-dimensional array of intersecting rows and columns of said regions, each of said regions being programmable to perform any of a plurality of logic functions on a plurality of logic region input signals applied to the logic region to produce at least one logic region output signal; a plurality of interconnection conductors associated with each of the rows and configured to convey signals to, from, and/or between the logic regions in the associated row; at least one programmable logic connector respectively associated with each of the interconnection conductors and configured to programmably select any of a plurality of PLC input signals applied to the programmable logic connector for application to the interconnection conductor associated with that programmable logic connector, at least one of the PLC input signals applied to each programmable logic connector being the logic region output signal of a logic region in the row associated with the interconnection conductor that the programmable logic connector applies a signal to, and at least one other of the PLC input signals applied to each programmable logic connector being the logic region output signal of a logic region in another row which is applied to the programmable logic connector substantially directly from the logic region in the other row; and a driver associated with each programmable logic connector and configured to strengthen the signal that the programmable logic connector applies to the associated interconnection conductor.

Claim 9

The device defined in claim 5 wherein the driver is a programmably controlled tri-state driver.

Claim 10

A programmable logic integrated circuit device comprising: a plurality of regions of programmable logic disposed on the device in a two-dimensional array of intersecting rows and columns of said regions, each of said regions being programmable to perform any of a plurality of logic functions on a plurality of logic region input signals applied to the logic region to produce at least one logic region output signal; a plurality of interconnection conductors associated with each of the rows and configured to convey signals to, from, and/or between the logic regions in the associated row; and at least one programmable logic connector respectively associated with each of the interconnection conductors and configured to programmably select any of a plurality of PLC input signals applied to the programmable logic connector for application to the interconnection conductor associated with that programmable logic connector, at least one of the PLC input signals applied to each programmable logic connector being the logic region output signal of a logic region in the row associated with the interconnection conductor that the programmable logic connector applies a signal to, and at least one other of the PLC input signals applied to each programmable logic connector being the logic region output signal of a logic region in another row which is applied to the programmable logic connector substantially directly from the logic region in the other row, wherein each logic region includes: combinatorial logic circuitry which is programmable to produce a first intermediate signal which is any of a plurality of logical combinations of the logic region input signals applied to the logic region; register circuitry configured to produce a second intermediate signal which is the result of registering the first intermediate signal; and output signal selection circuitry configured to programmably select the logic region output signal from one of the first and second intermediate signals.

Claim 11

A programmable logic integrated circuit device comprising: a plurality of regions of programmable logic disposed on the device in a two-dimensional array of intersecting rows and columns of said regions, each of said regions being programmable to perform any of a plurality of logic functions on a plurality of logic region input signals applied to the logic region to produce at least one logic region output signal; a plurality of interconnection conductors associated with each of the rows and configured to convey signals to, from, and/or between the logic regions in the associated row; and at least one programmable logic connector respectively associated with each of the interconnection conductors and configured to programmably select any of a plurality of PLC input signals applied to the programmable logic connector for application to the interconnection conductor associated with that programmable logic connector, at least one of the PLC input signals applied to each programmable logic connector being the logic region output signal of a logic region in the row associated with the interconnection conductor that the programmable logic connector applies a signal to, and at least one other of the PLC input signals applied to each programmable logic connector being the logic region output signal of a logic region in another row which is applied to the programmable logic connector substantially directly from the logic region in the other row, wherein each logic region includes: combinatorial logic circuitry which is programmable to produce a first intermediate signal which is any of a plurality of logical combinations of the logic region input signals applied to the logic region; register circuitry configured to produce a second intermediate signal which is the result of registering the first intermediate signal; and output signal selection circuitry configured to programmably select the logic region output signal from one of the first and second intermediate signals.

Claim 12

A programmable logic integrated circuit device comprising: a plurality of regions of programmable logic disposed on the device in a two-dimensional array of intersecting rows and columns of said regions, each of said regions being programmable to perform any of a plurality of logic functions on a plurality of logic region input signals applied to the logic region to produce at least one logic region output signal; a plurality of interconnection conductors associated with each of the rows and configured to convey signals to, from, and/or between the logic regions in the associated row; and at least one programmable logic connector respectively associated with each of the interconnection conductors and configured to programmably select any of a plurality of PLC input signals applied to the programmable logic connector for application to the interconnection conductor associated with that programmable logic connector, at least one of the PLC input signals applied to each programmable logic connector being the logic region output signal of a logic region in the row associated with the interconnection conductor that the programmable logic connector applies a signal to, and at least one other of the PLC input signals applied to each programmable logic connector being the logic region output signal of a logic region in another row which is applied to the programmable logic connector substantially directly from the logic region in the other row, wherein each conductor in a subplurality of the interconnection conductors associated with each row extends adjacent a respective different one of a plurality of subsets of the logic regions in that row, the logic regions in each subset being adjacent to one another, and wherein the interconnection conductor associated with each programmable logic connector is one of the conductors in the subplurality.

Claim 13

A programmable logic integrated circuit device comprising: a plurality of regions of programmable logic disposed on the device in a two-dimensional array of intersecting rows and columns of said regions, each of said regions being programmable to perform any of a plurality of logic functions on a plurality of logic region input signals applied to the logic region to produce at least one logic region output signal; a plurality of interconnection conductors associated with each of the rows and configured to convey signals to, from, and/or between the logic regions in the associated row; and at least one programmable logic connector respectively associated with each of the interconnection conductors and configured to programmably select any of a plurality of PLC input signals applied to the programmable logic connector for application to the interconnection conductor associated with that programmable logic connector, at least one of the PLC input signals applied to each programmable logic connector being the logic region output signal of a logic region in the row associated with the interconnection conductor that the programmable logic connector applies a signal to, and at least one other of the PLC input signals applied to each programmable logic connector being the logic region output signal of a logic region in another row which is applied to the programmable logic connector substantially directly from the logic region in the other row, wherein each conductor in a subplurality of the interconnection conductors associated with each row extends adjacent a respective different one of a plurality of subsets of the logic regions in that row, the logic regions in each subset being adjacent to one another, and wherein the interconnection conductor associated with each programmable logic connector is one of the conductors in the subplurality.

Claim 14

The device defined in claim 8 wherein each programmable logic connector is operatively connected to an endpoint of the associated interconnection conductor.

Claim 15

A digital processing system comprising: processing circuitry; a memory coupled to said processing circuitry; and a programmable logic integrated circuit device as defined in claim 1 coupled to the processing circuitry and the memory.

Claim 16

A printed circuit board on which is mounted the programmable logic integrated circuit device as defined in claim 1 .

Claim 17

The printed circuit board defined in claim 11 further comprising: the memory mounted on the printed circuit board and coupled to the programmable logic integrated circuit device.

Claim 18

The printed circuit board defined in claim 11 further comprising: processing circuitry mounted on the printed circuit board and coupled to the programmable logic integrated circuit device.

Claim 19

A programmable logic integrated circuit device comprising: a plurality of regions of programmable logic disposed on the device in a two-dimensional array of intersecting rows and columns of said regions, each of said regions being programmable to perform any of a plurality of logic functions on a plurality of logic region input signals applied to the logic region to produce at least one logic region output signal; a plurality of interconnection conductors associated with each of the rows and configured to convey signals to, from, and/or between the logic regions in the associated row; and programmable logic connector circuitry associated with each of the logic regions and configured to programmably select a signal applied to one of a plurality of PLC input terminals of the programmable logic connector circuitry for application to the associated logic region as a logic region input signal, at least a first one of the PLC input terminals being connected to an interconnection conductor associated with the row that includes that logic region, and at least a second one of the PLC input terminals being connected to an interconnection conductor associated with another row that is adjacent to the row that includes that logic region.

Claim 20

A programmable logic integrated circuit device comprising: a plurality of regions of programmable logic disposed on the device in a two-dimensional array of intersecting rows and columns of said regions, each of said regions being programmable to perform any of a plurality of logic functions on a plurality of logic region input signals applied to the logic region to produce at least one logic region output signal; a plurality of interconnection conductors associated with each of the rows and configured to convey signals to, from, and/or between the logic regions in the associated row; and programmable logic connector circuitry associated with each of the logic regions and configured to programmably select a signal applied to one of a plurality of PLC input terminals of the programmable logic connector circuitry for application to the associated logic region as a logic region input signal, at least a first one of the PLC input terminals being connected to an interconnection conductor associated with the row that includes that logic region, and at least a second one of the PLC input terminals being connected to an interconnection conductor associated with another row that is adjacent to the row that includes that logic region.

Claim 21

A programmable logic integrated circuit device comprising: a plurality of regions of programmable logic disposed on the device in a two-dimensional array of intersecting rows and columns of said regions, each of said regions being programmable to perform any of a plurality of logic functions on a plurality of logic region input signals applied to the logic region to produce at least one logic region output signal; a plurality of interconnection conductors associated with each of the rows and configured to convey signals to, from, and/or between the logic regions in the associated row; programmable logic connector circuitry associated with each of the logic regions and configured to programmably select a signal applied to one of a plurality of PLC input terminals of the programmable logic connector circuitry for application to the associated logic region as a logic region input signal, at least a first one of the PLC input terminals being connected to an interconnection conductor associated with the row that includes that logic region, and at least a second one of the PLC input terminals being connected to an interconnection conductor associated with another row that is adjacent to the row that includes that logic region; and second programmable logic connector circuitry associated with each of the logic regions and configured to programmably select a signal applied to one of a plurality of second PLC input terminals of the second programmable logic connector circuitry for application to the associated logic region as another logic region input signal, at least a first one of the second PLC input terminals being connected to an interconnection conductor associated with the row that includes that logic region, and at least a second one of the second PLC input terminals being connected to an interconnection conductor associated with a third row that is adjacent to the row that includes that logic region.

Claim 22

A programmable logic integrated circuit device comprising: a plurality of regions of programmable logic disposed on the device in a two-dimensional array of intersecting rows and columns of said regions, each of said regions being programmable to perform any of a plurality of logic functions on a plurality of logic region input signals applied to the logic region to produce at least one logic region output signal; a plurality of interconnection conductors associated with each of the rows and configured to convey signals to, from, and/or between the logic regions in the associated row; programmable logic connector circuitry associated with each of the logic regions and configured to programmably select a signal applied to one of a plurality of PLC input terminals of the programmable logic connector circuitry for application to the associated logic region as a logic region input signal, at least a first one of the PLC input terminals being connected to an interconnection conductor associated with the row that includes that logic region, and at least a second one of the PLC input terminals being connected to an interconnection conductor associated with another row that is adjacent to the row that includes that logic region; and second programmable logic connector circuitry associated with each of the logic regions and configured to programmably select a signal applied to one of a plurality of second PLC input terminals of the second programmable logic connector circuitry for application to the associated logic region as another logic region input signal, at least a first one of the second PLC input terminals being connected to an interconnection conductor associated with the row that includes that logic region, and at least a second one of the second PLC input terminals being connected to an interconnection conductor associated with a third row that is adjacent to the row that includes that logic region.

Claim 23

A programmable logic integrated circuit device comprising: a plurality of regions of programmable logic disposed on the device in a two-dimensional array of intersecting rows and columns of said regions, each of said regions being programmable to perform any of a plurality of logic functions on a plurality of logic region input signals applied to the logic region to produce at least one logic region output signal; a plurality of interconnection conductors associated with each of the rows and configured to convey signals to, from, and/or between the logic regions in the associated row; and programmable logic connector circuitry associated with each of the logic regions and configured to programmably select a signal applied to one of a plurality of PLC input terminals of the programmable logic connector circuitry for application to the associated logic region as a logic region input signal, at least a first one of the PLC input terminals being connected to an interconnection conductor associated with the row that includes that logic region, and at least a second one of the PLC input terminals being connected to an interconnection conductor associated with another row that is adjacent to the row that includes that logic region, wherein the PLC input terminals of the programmable logic connector circuitry associated with each of the logic regions are connected to only a subset of the interconnection conductors associated with the row that includes that logic region and the row adjacent to the row that includes that logic region.

Claim 24

A programmable logic integrated circuit device comprising: a plurality of regions of programmable logic disposed on the device in a two-dimensional array of intersecting rows and columns of said regions, each of said regions being programmable to perform any of a plurality of logic functions on a plurality of logic region input signals applied to the logic region to produce at least one logic region output signal; a plurality of interconnection conductors associated with each of the rows and configured to convey signals to, from, and/or between the logic regions in the associated row; and programmable logic connector circuitry associated with each of the logic regions and configured to programmably select a signal applied to one of a plurality of PLC input terminals of the programmable logic connector circuitry for application to the associated logic region as a logic region input signal, at least a first one of the PLC input terminals being connected to an interconnection conductor associated with the row that includes that logic region, and at least a second one of the PLC input terminals being connected to an interconnection conductor associated with another row that is adjacent to the row that includes that logic region, wherein the PLC input terminals of the programmable logic connector circuitry associated with each of the logic regions are connected to only a subset of the interconnection conductors associated with the row that includes that logic region and the row adjacent to the row that includes that logic region.

Claim 25

The device defined in claim 15 wherein the PLC input terminals of the programmable logic connector circuitry associated with each of the logic regions are connected to only a subset of the interconnection conductors associated with the row that includes that logic region and the row adjacent to the row that includes that logic region, and wherein the second PLC input terminals of the second programmable logic connector circuitry associated with each of logic regions are connected to only a second subset of the interconnection conductors associated with the row that includes that logic region and the third row that is adjacent to the row that includes that logic region.

Claim 26

A programmable logic integrated circuit device comprising: a row of regions of programmable logic, each being programmable to perform any of a plurality of logic functions on a plurality of logic region input signals applied to the logic region to produce at least one logic region output signal; a first conductor associated with each of the logic regions and extending from the associated logic region adjacent a first subplurality of others of the logic regions that are adjacent to the associated logic region on a first side of the associated logic region; a second conductor associated with each of the logic regions and extending from the associated logic region adjacent a second subplurality of still others of the logic regions that are adjacent to the associated logic region on a second side of the associated logic region; first programmable logic connector circuitry associated with each of the logic regions and configured to selectively apply the logic region output signal of the associated logic region to either or both of the first and second conductors associated with that logic region; and second programmable logic connector circuitry associated with at least some of the logic regions that each of the first and second conductors is adjacent to and configured to selectively apply a signal on that first or second conductor to the associated logic regions as a logic region input signal.

Claim 27

A programmable logic integrated circuit device comprising: a row of regions of programmable logic, each being programmable to perform any of a plurality of logic functions on a plurality of logic region input signals applied to the logic region to produce at least one logic region output signal; a first conductor associated with each of the logic regions and extending from the associated logic region adjacent a first subplurality of others of the logic regions that are adjacent to the associated logic region on a first side of the associated logic region; a second conductor associated with each of the logic regions and extending from the associated logic region adjacent a second subplurality of still others of the logic regions that are adjacent to the associated logic region on a second side of the associated logic region; first programmable logic connector circuitry associated with each of the logic regions and configured to selectively apply the logic region output signal of the associated logic region to either or both of the first and second conductors associated with that logic region; and second programmable logic connector circuitry associated with at least some of the logic regions that each of the first and second conductors is adjacent to and configured to selectively apply a signal on that first or second conductor to the associated logic regions as a logic region input signal.

Claim 28

The device defined in claim 18 wherein each of the first subpluralities includes approximately a same first number of the logic regions.

Claim 29

The device defined in claim 18 wherein each of the second subpluralities includes approximately a same second number of the logic region.

Claim 30

The device defined in claim 18 wherein each of the first and second subpluralities includes approximately a same number of the logic regions.

Claim 31

The device defined in claim 18 wherein each of the logic regions is programmable to produce a plurality of logic region output signals, and wherein the first programmable logic connector circuitry associated with each of the logic regions is further configured to alternatively selectively apply different ones of the logic region output signals of the associated logic region to the first and second conductors associated with that logic region.

Claim 32

A programmable logic integrated circuit device comprising: a row of regions of programmable logic, each being programmable to perform any of a plurality of logic functions on a plurality of logic region input signals applied to the logic region to produce at least one logic region output signal; a first conductor associated with each of the logic regions and extending from the associated logic region adjacent a first subplurality of others of the logic regions that are adjacent to the associated logic region on a first side of the associated logic region; a second conductor associated with each of the logic regions and extending from the associated logic region adjacent a second subplurality of still others of the logic regions that are adjacent to the associated logic region on a second side of the associated logic region; first programmable logic connector circuitry associated with each of the logic regions and configured to selectively apply the logic region output signal of the associated logic region to either or both of the first and second conductors associated with that logic region; and second programmable logic connector circuitry associated with at least some of the logic regions that each of the first and second conductors is adjacent to and configured to selectively apply a signal on that first or second conductor to the associated logic regions as a logic region input signal, wherein each of the logic regions is programmable to produce a plurality of logic region output signals, wherein the first programmable logic connector circuitry associated with each of the logic regions is further configured to alternatively selectively apply different ones of the logic region output signals of the associated logic region to the first and second conductors associated with that logic region, and wherein the first programmable logic connector circuitry associated with each of the logic regions is still further configured to alternatively selectively apply any of multiple ones of the logic region output signals of the associated logic region to either of the first and second conductors associated with that logic region.

Claim 33

A programmable logic integrated circuit device comprising: a row of regions of programmable logic, each being programmable to perform any of a plurality of logic functions on a plurality of logic region input signals applied to the logic region to produce at least one logic region output signal; a first conductor associated with each of the logic regions and extending from the associated logic region adjacent a first subplurality of others of the logic regions that are adjacent to the associated logic region on a first side of the associated logic region; a second conductor associated with each of the logic regions and extending from the associated logic region adjacent a second subplurality of still others of the logic regions that are adjacent to the associated logic region on a second side of the associated logic region; first programmable logic connector circuitry associated with each of the logic regions and configured to selectively apply the logic region output signal of the associated logic region to either or both of the first and second conductors associated with that logic region; and second programmable logic connector circuitry associated with at least some of the logic regions that each of the first and second conductors is adjacent to and configured to selectively apply a signal on that first or second conductor to the associated logic regions as a logic region input signal, wherein each of the logic regions is programmable to produce a plurality of logic region output signals, wherein the first programmable logic connector circuitry associated with each of the logic regions is further configured to alternatively selectively apply different ones of the logic region output signals of the associated logic region to the first and second conductors associated with that logic region, and wherein the first programmable logic connector circuitry associated with each of the logic regions is still further configured to alternatively selectively apply any of multiple ones of the logic region output signals of the associated logic region to either of the first and second conductors associated with that logic region.

Claim 34

The device defined in claim 18 wherein the second programmable logic circuitry is associated with all of the logic regions that each of the first and second conductors is adjacent to.

Claim 35

A programmable logic integrated circuit device comprising: a row of regions of programmable logic, each being programmable to perform any of a plurality of logic functions on a plurality of logic region input signals applied to the logic region to produce at least one logic region output signal; a first conductor associated with each of the logic regions and extending from the associated logic region adjacent a first subplurality of others of the logic regions that are adjacent to the associated logic region on a first side of the associated logic region; a second conductor associated with each of the logic regions and extending from the associated logic region adjacent a second subplurality of still others of the logic regions that are adjacent to the associated logic region on a second side of the associated logic region; first programmable logic connector circuitry associated with each of the logic regions and configured to selectively apply the logic region output signal of the associated logic region to either or both of the first and second conductors associated with that logic region; and second programmable logic connector circuitry associated with at least some of the logic regions that each of the first and second conductors is adjacent to and configured to selectively apply a signal on that first or second conductor to the associated logic regions as a logic region input signal, wherein the row is one of a plurality of similarly constructed, parallel rows, and wherein the first programmable logic connector circuitry associated with each of the logic regions is further configured to alternatively selectively apply to either or both of the first and second conductors associated with that logic region a logic region output signal from another logic region in a row adjacent to the row that includes that logic region.

Claim 36

A programmable logic integrated circuit device comprising: a row of regions of programmable logic, each being programmable to perform any of a plurality of logic functions on a plurality of logic region input signals applied to the logic region to produce at least one logic region output signal; a first conductor associated with each of the logic regions and extending from the associated logic region adjacent a first subplurality of others of the logic regions that are adjacent to the associated logic region on a first side of the associated logic region; a second conductor associated with each of the logic regions and extending from the associated logic region adjacent a second subplurality of still others of the logic regions that are adjacent to the associated logic region on a second side of the associated logic region; first programmable logic connector circuitry associated with each of the logic regions and configured to selectively apply the logic region output signal of the associated logic region to either or both of the first and second conductors associated with that logic region; and second programmable logic connector circuitry associated with at least some of the logic regions that each of the first and second conductors is adjacent to and configured to selectively apply a signal on that first or second conductor to the associated logic regions as a logic region input signal, wherein the row is one of a plurality of similarly constructed, parallel rows, and wherein the first programmable logic connector circuitry associated with each of the logic regions is further configured to alternatively selectively apply to either or both of the first and second conductors associated with that logic region a logic region output signal from another logic region in a row adjacent to the row that includes that logic region.

Claim 37

The device defined in claim 25 wherein the another logic region associated with each logic region is substantially aligned with the logic region in a column of logic regions that is substantially perpendicular to the rows of logic regions.

Claim 38

A digital processing system comprising: processing circuitry; a memory coupled to said processing circuitry; and a programmable logic integrated circuit device as defined in claim 18 coupled to the processing circuitry and the memory.

Claim 39

A printed circuit board on which is mounted the programmable logic integrated circuit device as defined in claim 18 .

Claim 40

The printed circuit board defined in claim 28 further comprising: a memory mounted on the printed circuit board and coupled to the programmable logic integrated circuit device.

Claim 41

The printed circuit board defined in claim 28 further comprising: processing circuitry mounted on the printed circuit board and coupled to the programmable logic integrated circuit device.

Claim 42

A programmable logic integrated circuit device comprising: a plurality of regions of programmable logic disposed on the device in a two-dimensional array of intersecting rows and columns of such regions, each of the regions being programmable to perform any of a plurality of logic functions on a plurality of logic region input signals applied to the logic region to produce at least one logic region output signal; a plurality of interconnection conductors associated with each of the rows and configured to convey signals to, from, and/or between the logic regions in the associated row; a plurality of region-feeding conductors associated with each of the logic regions and configured to bring signals to the associated logic region as at least some of the logic region input signals of the associated logic region; first programmable logic connector circuitry associated with each of the logic regions and configured to selectively apply to the region-feeding conductors associated with that logic region signals from the interconnection conductors associated with the row that includes that logic region; and second programmable logic connector circuitry associated with each of the logic regions and configured to selectively apply signals from the region-feeding conductors associated with that logic region to the region-feeding conductors that are associated with another vertically adjacent logic region in the column that includes that logic region.

Claim 43

A programmable logic integrated circuit device comprising: a plurality of regions of programmable logic disposed on the device in a two-dimensional array of intersecting rows and columns of such regions, each of the regions being programmable to perform any of a plurality of logic functions on a plurality of logic region input signals applied to the logic region to produce at least one logic region output signal; a plurality of interconnection conductors associated with each of the rows and configured to convey signals to, from, and/or between the logic regions in the associated row; a plurality of region-feeding conductors associated with each of the logic regions and configured to bring signals to the associated logic region as at least some of the logic region input signals of the associated logic region; first programmable logic connector circuitry associated with each of the logic regions and configured to selectively apply to the region-feeding conductors associated with that logic region signals from the interconnection conductors associated with the row that includes that logic region; and second programmable logic connector circuitry associated with each of the logic regions and configured to selectively apply signals from the region-feeding conductors associated with that logic region to the region-feeding conductors that are associated with another vertically adjacent logic region in the column that includes that logic region.

Claim 44

A programmable logic integrated circuit device comprising: a plurality of regions of programmable logic disposed on the device in a two-dimensional array of intersecting rows and columns of such regions, each of the regions being programmable to perform any of a plurality of logic functions on a plurality of logic region input signals applied to the logic region to produce at least one logic region output signal; a plurality of interconnection conductors associated with each of the rows and configured to convey signals to, from, and/or between the logic regions in the associated row; a plurality of region-feeding conductors associated with each of the logic regions and configured to bring signals to the associated logic region as at least some of the logic region input signals of the associated logic region; first programmable logic connector circuitry associated with each of the logic regions and configured to selectively apply to the region-feeding conductors associated with that logic region signals from the interconnection conductors associated with the row that includes that logic region; second programmable logic connector circuitry associated with each of the logic regions and configured to selectively apply signals from the region-feeding conductors associated with that logic region to the region-feeding conductors that are associated with another adjacent logic region in the column that includes that logic region; and third programmable logic connector circuitry associated with each of the logic regions and configured to selectively apply signals from the region-feeding conductors associated with that logic region to the region-feeding conductors that are associated with a further adjacent logic region in the column that includes that logic region but on the other side of that logic region from the another logic region associated with that logic region.

Claim 45

A programmable logic integrated circuit device comprising: a plurality of regions of programmable logic disposed on the device in a two-dimensional array of intersecting rows and columns of such regions, each of the regions being programmable to perform any of a plurality of logic functions on a plurality of logic region input signals applied to the logic region to produce at least one logic region output signal; a plurality of interconnection conductors associated with each of the rows and configured to convey signals to, from, and/or between the logic regions in the associated row; a plurality of region-feeding conductors associated with each of the logic regions and configured to bring signals to the associated logic region as at least some of the logic region input signals of the associated logic region; first programmable logic connector circuitry associated with each of the logic regions and configured to selectively apply to the region-feeding conductors associated with that logic region signals from the interconnection conductors associated with the row that includes that logic region; second programmable logic connector circuitry associated with each of the logic regions and configured to selectively apply signals from the region-feeding conductors associated with that logic region to the region-feeding conductors that are associated with another adjacent logic region in the column that includes that logic region; and third programmable logic connector circuitry associated with each of the logic regions and configured to selectively apply signals from the region-feeding conductors associated with that logic region to the region-feeding conductors that are associated with a further adjacent logic region in the column that includes that logic region but on the other side of that logic region from the another logic region associated with that logic region.

Claim 46

A programmable logic integrated circuit device comprising: a plurality of regions of programmable logic disposed on the device in a two-dimensional array of intersecting rows and columns of such regions, each of the regions being programmable to perform any of a plurality of logic functions on a plurality of logic region input signals applied to the logic region to produce at least one logic region output signal; a plurality of interconnection conductors associated with each of the rows and configured to convey signals to, from, and/or between the logic regions in the associated row; a plurality of region-feeding conductors associated with each of the logic regions and configured to bring signals to the associated logic region as at least some of the logic region input signals of the associated logic region; first programmable logic connector circuitry associated with each of the logic regions and configured to selectively apply to the region-feeding conductors associated with that logic region signals from the interconnection conductors associated with the row that includes that logic region; second programmable logic connector circuitry associated with each of the logic regions and configured to selectively apply signals from the region-feeding conductors associated with that logic region to the region-feeding conductors that are associated with another adjacent logic region in the column that includes that logic region; a local feedback conductor associated with each of the logic regions and configured to receive the logic region output signal of the associated logic region for application to the associated logic region as at least one of the logic region input signals of the associated logic region; and third programmable logic connector circuitry associated with each of the logic regions and configured to selectively apply a signal from the local feedback conductor that is associated with that logic region to at least one of the region-feeding conductors that are associated with another adjacent logic region in the column that includes that logic region.

Claim 47

A programmable logic integrated circuit device comprising: a plurality of regions of programmable logic disposed on the device in a two-dimensional array of intersecting rows and columns of such regions, each of the regions being programmable to perform any of a plurality of logic functions on a plurality of logic region input signals applied to the logic region to produce at least one logic region output signal; a plurality of interconnection conductors associated with each of the rows and configured to convey signals to, from, and/or between the logic regions in the associated row; a plurality of region-feeding conductors associated with each of the logic regions and configured to bring signals to the associated logic region as at least some of the logic region input signals of the associated logic region; first programmable logic connector circuitry associated with each of the logic regions and configured to selectively apply to the region-feeding conductors associated with that logic region signals from the interconnection conductors associated with the row that includes that logic region; second programmable logic connector circuitry associated with each of the logic regions and configured to selectively apply signals from the region-feeding conductors associated with that logic region to the region-feeding conductors that are associated with another adjacent logic region in the column that includes that logic region; a local feedback conductor associated with each of the logic regions and configured to receive the logic region output signal of the associated logic region for application to the associated logic region as at least one of the logic region input signals of the associated logic region; and third programmable logic connector circuitry associated with each of the logic regions and configured to selectively apply a signal from the local feedback conductor that is associated with that logic region to at least one of the region-feeding conductors that are associated with another adjacent logic region in the column that includes that logic region.

Claim 48

The device defined in claim 33 further comprising: fourth programmable logic connector circuitry associated with each of the logic regions and configured to selectively apply a signal from the local feedback conductor that is associated with that logic region to at least one of the region-feeding conductors that are associated with a further logic region in the column that includes that logic region but on the other side of that logic region from the another logic region associated with that logic region.