US6356567B2
Expired / Lapsed
US
⏱️ 0.0 years remaining
Embedded clock recovery and difference filtering for an MPEG-2 compliant transport stream
Assignee: MediaTek Inc
•
Filing: 1997-09-26
•
Granted: 2002-03-12
•
Expires: 2017-09-26
Abstract
Abstract A method of decoding a bitstream having an embedded clock, where the clock reference data is recovered from the bit stream. The clock reference data is combined, typically subtracted, from the system time clock to generate a result. This result is input to a pulse width modulator to form a pulse train, which is used to generate an input to a timing device.
Inventors
- 👤 Richard E. Anderson
- 👤 Eric M. Foster
- 👤 Mark R. Hodges
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 04:24
CPC Classifications
H; H04; H04J; H04J3/00; H04J3/02; H04J3/06; H04J3/062; H04J3/0632; H04N; H04N21/00; H04N21/20; H04N21/23; H04N21/236; H04N21/2368; H04N21/40; H04N21/41; H04N21/426; H04N21/43; H04N21/4302; H04N21/4305; H04N21/434; H04N21/4341; H04N5/00; H04N5/04
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
128 words
A method of decoding a bit stream in a communications system, said bit stream having an embedded clock, said method comprising: recovering program clock reference data from the bit stream, flagging information in said bit stream corresponding to a time base discontinuity or a channel change of said system, initializing system time clock data with a first program clock reference data, comparing the bit stream clock reference data and the system time clock data, placing a result of said comparing step in a pulse width modulator to form a pulse train, generating an input to a timing device based on the pulse train for synchronizing said system time clock, and decoding said bit stream responsive to said timing device and said flagged time base discontinuity or channel change.
Claim 2
Independent Claim
128 words
A method of decoding a bit stream in a communications system, said bit stream having an embedded clock, said method comprising: recovering program clock reference data from the bit stream, flagging information in said bit stream corresponding to a time base discontinuity or a channel change of said system, initializing system time clock data with a first program clock reference data, comparing the bit stream clock reference data and the system time clock data, placing a result of said comparing step in a pulse width modulator to form a pulse train, generating an input to a timing device based on the pulse train for synchronizing said system time clock, and decoding said bit stream responsive to said timing device and said flagged time base discontinuity or channel change.
Claim 3
Dependent Claim
49 words
The method of claim 1 , wherein said comparing step includes: subtracting the bit stream clock reference data from the system time clock (STC) data to derive a difference, and comparing the difference obtained in said subtracting step to a threshold to determine if clock frequency correction is required.
Claim 4
Dependent Claim
32 words
The method of claim 2 , comprising: placing the difference between the program clock reference data from the system time clock data in said pulse width modulator to form the pulse train.
Claim 5
Independent Claim
121 words
A method of decoding a bitstream having an embedded clock including program clock reference (PCR), comprising recovering program clock reference data from the bit stream, initializing system time clock data with a first program clock reference data, performing subtraction on the bit stream clock reference data and the system time clock (STC) data from a timing device to derive a difference, placing the difference in a pulse width modulator (PWM) to form a pulse train, generating an input to said timing device therefrom whereby said timing device is synchronized with said program clock reference, generating an interrupt if the magnitude of the difference between the PCR and the STC exceeds a threshold and decoding said bitstream responsive to said timing device.
Claim 6
Independent Claim
121 words
A method of decoding a bitstream having an embedded clock including program clock reference (PCR), comprising recovering program clock reference data from the bit stream, initializing system time clock data with a first program clock reference data, performing subtraction on the bit stream clock reference data and the system time clock (STC) data from a timing device to derive a difference, placing the difference in a pulse width modulator (PWM) to form a pulse train, generating an input to said timing device therefrom whereby said timing device is synchronized with said program clock reference, generating an interrupt if the magnitude of the difference between the PCR and the STC exceeds a threshold and decoding said bitstream responsive to said timing device.
Claim 7
Dependent Claim
31 words
The method of claim 2 , further comprising: incrementing a register of the pulse width modulator if the system time clock data is less than the bit stream clock reference data.
Claim 8
Dependent Claim
31 words
The method of claim 2 , further comprising: decrementing a register of the pulse width modulator if the system time clock data is greater than the bit stream clock reference data.
Claim 9
Dependent Claim
19 words
The method of claim 1 , further comprising: storing previous bit stream clock reference and system time clock values.
Claim 10
Dependent Claim
25 words
The method of claim 7 , further comprising: adjusting system clock frequency according to the stored bit stream clock reference and system time clock values.
Claim 11
Dependent Claim
23 words
The method of claim 4 , wherein said initializing step is performed after detection of said time base discontinuity or a channel change.
Claim 12
Dependent Claim
38 words
The method of claim 8 , wherein said stored bit stream clock reference and system time clock values are used to initialize said system clock data upon said detection of said time base discontinuity or said channel change.
References Cited (Backward Citations)
US5365272A
Cited
US5381181A
Cited
US5521922A
Cited
US5506904A
Cited
US5425101A
Cited
US5467342A
Cited
US5612981A
Cited
US5596581A
Cited
US5619501A
Cited
US5502493A
Cited
US5594492A
Cited
US5559999A
Cited
US5960006A
Cited
US5594660A
Cited
US5566089A
Cited
US5901149A
Cited
US5535216A
Cited
US5652749A
Cited
US5517250A
Cited
US5751721A
Cited
US5768326A
Cited
US5602920A
Cited
US5589415A
Cited
US5790543A
Cited
US5881114A
Cited
US5726989A
Cited
US5818539A
Cited
US5905732A
Cited
US5936968A
Cited
US6021449A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2005-03-11 | 2005-09-10 | 2006-03-12 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2009-03-11 | 2009-09-10 | 2010-03-12 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2013-03-11 | 2013-09-10 | 2014-03-12 | $7700.00 | Window Closed / Lapsed |