Patent US6344994B1 successfully refreshed from Google Patents.
US6344994B1
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Data retention characteristics as a result of high temperature bake
Assignee: Longitude Flash Memory Solutions Ltd
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Filing: 2001-02-28
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Granted: 2002-02-05
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Expires: 2021-02-28
Abstract
Abstract Dummy wordlines are provided between gaps of blocks of memory cells to compensate for higher charge loss at higher stress temperatures exhibited at edge wordlines of blocks of memory cells having large gaps. The dummy wordlines minimize the gap between the blocks. The dummy wordlines can be positioned between the blocks. Alternatively, the wordline width for the last block or sector wordline can be changed or different nitride used with less conductance in high temperatures. The dummy wordlines are typically ignored in normal operations on the memory.
Inventors
- 👤 Darlene G. Hamilton
- 👤 Yider Wu
- 👤 Michael Han
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 09:38
CPC Classifications
G; G11; G11C; G11C16/00; G11C16/02; G11C16/06; G11C16/34; G11C16/3404; G11C16/3409; G11C11/00; G11C11/56; G11C11/5671; G11C16/04; G11C16/0466; G11C16/0475; G11C16/3436; G11C16/344; G11C16/3445; G11C16/3454; G11C5/00; G11C5/06; G11C5/063; G11C16/10
Claims Analysis
Total Claims: 31
Claim 1
Independent Claim
93 words
A flash memory device having a plurality of dual bit memory devices formed from an ONO stack layer, the device comprising: a first memory portion formed from an ONO stack layer, the first memory portion having a plurality of wordlines; a second memory portion formed from the ONO stack layer, the second memory portion having a plurality of wordlines; and a dummy wordline formed in a gap located between the first memory portion and the second memory portion, the dummy wordline facilitating reduction of charge rate on edge wordlines located adjacent the gap.
Claim 2
Dependent Claim
93 words
A flash memory device having a plurality of dual bit memory devices formed from an ONO stack layer, the device comprising: a first memory portion formed from an ONO stack layer, the first memory portion having a plurality of wordlines; a second memory portion formed from the ONO stack layer, the second memory portion having a plurality of wordlines; and a dummy wordline formed in a gap located between the first memory portion and the second memory portion, the dummy wordline facilitating reduction of charge rate on edge wordlines located adjacent the gap.
Claim 3
Dependent Claim
32 words
The device of claim 1 , further comprising a plurality of memory portions aligned along the ONO stack layer wherein a dummy wordline is located in a gap between adjacent memory portions.
Claim 4
Dependent Claim
39 words
The device of claim 2 , the plurality of memory portions having a first end and a second end wherein a dummy wordline is located alongside the first end and a dummy wordline is located alongside the second end.
Claim 5
Dependent Claim
20 words
The device of claim 1 , the first memory portion and the second memory portion being sectors of an array.
Claim 6
Dependent Claim
33 words
The device of claim 1 , the first and second memory portion each having a plurality of wordlines running parallel to the gaps and a plurality of bitlines running perpendicular to the gap.
Claim 7
Dependent Claim
74 words
The device of claim 5 , further comprising contacts formed in each bitline at a first end and a second end of the first memory portion and contacts formed in each bitline at a first end and a second end of the second memory portion, the dummy wordline being located between the contacts at the second end of the first memory portion and the contacts at the first end of the second memory portion.
Claim 8
Dependent Claim
29 words
The device of claim 6 , the dummy wordline being floated during normal operation to allow the dummy wordline to be shorted to the contacts without causing electrical currents.
Claim 9
Dependent Claim
22 words
The device of claim 1 , the dummy wordline reducing charging due to an etching process occurring during fabrication of the device.
Claim 10
Dependent Claim
84 words
A flash memory device having a plurality of dual bit memory devices formed from an ONO stack layer, the device comprising: a block of memory formed from an ONO stack layer; a plurality of wordlines connecting rows of memory cells wherein a first edge wordline at a first end of the block and a second edge wordline at a second end of the block are formed of a thickness smaller than the remaining wordlines; and a plurality of bitlines connecting columns of memory cells.
Claim 11
Dependent Claim
84 words
A flash memory device having a plurality of dual bit memory devices formed from an ONO stack layer, the device comprising: a block of memory formed from an ONO stack layer; a plurality of wordlines connecting rows of memory cells wherein a first edge wordline at a first end of the block and a second edge wordline at a second end of the block are formed of a thickness smaller than the remaining wordlines; and a plurality of bitlines connecting columns of memory cells.
Claim 12
Dependent Claim
16 words
The device of claim 9 , the edge wordlines being actual wordlines of the memory block.
Claim 13
Dependent Claim
12 words
The device of claim 9 , the edge wordlines being dummy wordlines.
Claim 14
Dependent Claim
40 words
The device of claim 11 , at least one memory cell being connected to the edge wordlines, the at least one memory cell being programmed and erased with other memory cells during normal operation and being grounded during read operations.
Claim 15
Dependent Claim
18 words
The device of claim 9 , further comprising contacts formed at each end of the plurality of bitlines.
Claim 16
Independent Claim
109 words
A method of forming a flash memory device having a plurality of dual bit memory devices formed from an ONO stack layer, the method comprising: forming at least one memory block in an ONO stack layer; forming a plurality of wordlines connecting rows of memory cells in the at least one memory block wherein a first edge wordline at a first end of the at least one memory block and a second edge wordline formed at a second end of the at least one memory block are formed of a thickness smaller than the remaining plurality of wordlines; and forming a plurality of bitlines connecting columns of memory cells.
Claim 17
Independent Claim
109 words
A method of forming a flash memory device having a plurality of dual bit memory devices formed from an ONO stack layer, the method comprising: forming at least one memory block in an ONO stack layer; forming a plurality of wordlines connecting rows of memory cells in the at least one memory block wherein a first edge wordline at a first end of the at least one memory block and a second edge wordline formed at a second end of the at least one memory block are formed of a thickness smaller than the remaining plurality of wordlines; and forming a plurality of bitlines connecting columns of memory cells.
Claim 18
Dependent Claim
13 words
The method of claim 14 , the block of memory being a sector.
Claim 19
Dependent Claim
22 words
The method of claim 14 , the first and second edge wordlines being actual wordlines of the at least one memory block.
Claim 20
Dependent Claim
15 words
The method of claim 14 , the first and second edge wordlines being dummy wordlines.
Claim 21
Dependent Claim
43 words
The method of claim 16 , at least one memory cell being connected to the first and second edge wordlines, the at least one memory cell being programmed and erased with other memory cells during normal operation and being grounded during read operations.
Claim 22
Dependent Claim
67 words
A flash memory device having a plurality of dual bit memory devices formed from an ONO stack layer, the device comprising: means for forming a plurality of memory blocks in an ONO stack layer, the plurality of memory blocks having gaps therebetween; means for forming a plurality of wordlines connecting sets of memory cells; and means for reducing a charge rate on edge wordlines adjacent the gaps.
Claim 23
Dependent Claim
67 words
A flash memory device having a plurality of dual bit memory devices formed from an ONO stack layer, the device comprising: means for forming a plurality of memory blocks in an ONO stack layer, the plurality of memory blocks having gaps therebetween; means for forming a plurality of wordlines connecting sets of memory cells; and means for reducing a charge rate on edge wordlines adjacent the gaps.
Claim 24
Independent Claim
99 words
A method of forming a flash memory device having a plurality of dual bit memory devices formed from an ONO stack layer, the method comprising: forming a first memory portion and a second memory portion from an ONO stack layer, the first memory portion and the second memory portion having a gap therebetween; forming a plurality of wordlines for the first memory portion and the second memory portion that connect rows of dual bit memory devices; and forming a dummy wordline in the gap, the dummy wordline facilitating reduction of charge rate on edge wordlines located adjacent the gap.
Claim 25
Independent Claim
99 words
A method of forming a flash memory device having a plurality of dual bit memory devices formed from an ONO stack layer, the method comprising: forming a first memory portion and a second memory portion from an ONO stack layer, the first memory portion and the second memory portion having a gap therebetween; forming a plurality of wordlines for the first memory portion and the second memory portion that connect rows of dual bit memory devices; and forming a dummy wordline in the gap, the dummy wordline facilitating reduction of charge rate on edge wordlines located adjacent the gap.
Claim 26
Dependent Claim
33 words
The method of claim 20 , further comprising forming a plurality of memory portions aligned along the ONO stack layer wherein a dummy wordline is located in a gap between adjacent memory portions.
Claim 27
Dependent Claim
39 words
The method of claim 21 , the plurality of memory portions having a first end and a second end wherein a dummy wordline is located alongside the first end and a dummy wordline is located alongside the second end.
Claim 28
Dependent Claim
20 words
The method of claim 20 , the first memory portion and the second memory portion being sectors of an array.
Claim 29
Dependent Claim
33 words
The method of claim 20 , the first and second memory portion each having a plurality of wordlines running parallel to the gaps and a plurality of bitlines running perpendicular to the gap.
Claim 30
Dependent Claim
74 words
The method of claim 20 , further comprising forming contacts in each bitline at a first end and a second end of the first memory portion and forming contacts in each bitline at a first end and a second end of the second memory portion, the dummy wordline being located between the contacts at the second end of the first memory portion and the contacts at the first end of the second memory portion.
Claim 31
Dependent Claim
30 words
The method of claim 20 , further comprising floating the dummy wordline during normal operation to allow the dummy wordline to be shorted to the contacts without causing electrical currents.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2005-02-04 | 2005-08-06 | 2006-02-05 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2009-02-04 | 2009-08-06 | 2010-02-05 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2013-02-04 | 2013-08-06 | 2014-02-05 | $7700.00 | Window Closed / Lapsed |