US6343364B1
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method and device for local clock generation using universal serial bus downstream received signals DP and DM
Assignee: STMicroelectronics lnc USA
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Filing: 2000-07-13
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Granted: 2002-01-29
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Expires: 2020-07-13
Abstract
Abstract A method and device is disclosed for generating a local clock signal CLK1X (172) from Universal Synchronous Bus downstream-received differential signals DM and DP carrying the downstream received bit-serial signal. The method and device does not require the use of a crystal or resonator. Counters (312, 310, 305, 301) are used to determine a number of periods of a free-running high frequency clock signal (164) contained within in a known number of bit periods of the downstream received bit-serial signal (146). The counter values are divided by the known number of bit periods of the received bit-serial signal (146) to determine a bit period of the received bit-serial signal (146). The local clock signal (172) may be phase-locked with the received bit serial signal (146). The local clock period is updated on an ongoing manner by downstream known received traffic.
Inventors
- 👤 Robert A. Leydier
- 👤 Alain C. Pomet
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-03 05:35
CPC Classifications
G; G06; G06K; G06K19/00; G06K19/06; G06K19/067; G06K19/07; G06K19/077; G06K19/0772; G06K19/07733; G06F; G06F1/00; G06F1/04; G06F1/12; G06K7/00; G06K7/0008; H; H04; H04L; H04L7/00; H04L7/02; H04L7/033; H04L7/0331; H04L7/0337; H04L7/04; H04L7/10
Claims Analysis
Total Claims: 35
Claim 1
Independent Claim
146 words
A method for generating a local clock signal in a device using Universal Serial Bus downstream signals DP and DM, comprising; a) receiving the USB downstream differential signals DP and DM and generating a downstream bit-serial signal from the USB downstream signals; b) counting a number of cycles R of a free-running high frequency clock signal contained within a known number of bit periods S of the received downstream bit-serial signal; c) dividing the counted number of cycles R of the free-running high frequency clock signal by the known number of bit periods S of the received downstream bit-serial signal for determining a resultant number of the free-running high frequency clock cycles T contained within a single bit period of the received downstream bit-serial signal; and d) generating a local clock signal having a period equal to the number of free-running high frequency clock cycles T.
Claim 2
Independent Claim
146 words
A method for generating a local clock signal in a device using Universal Serial Bus downstream signals DP and DM, comprising; a) receiving the USB downstream differential signals DP and DM and generating a downstream bit-serial signal from the USB downstream signals; b) counting a number of cycles R of a free-running high frequency clock signal contained within a known number of bit periods S of the received downstream bit-serial signal; c) dividing the counted number of cycles R of the free-running high frequency clock signal by the known number of bit periods S of the received downstream bit-serial signal for determining a resultant number of the free-running high frequency clock cycles T contained within a single bit period of the received downstream bit-serial signal; and d) generating a local clock signal having a period equal to the number of free-running high frequency clock cycles T.
Claim 3
Dependent Claim
71 words
A method according to claim 1 wherein the step of generating the local clock signal comprises: a) counting the number of the free-running high frequency clock cycles T to generate a period of the local clock signal; and a) initializing the counting step when there is a data toggling in the received downstream bit serial signal for locking in phase the generated local clock with the received downstream bit serial signal.
Claim 4
Dependent Claim
36 words
A method according to claim 1 , wherein the step of generating the local clock signal further comprises updating the period of the local clock signal when a known received downstream bit serial pattern is recognized.
Claim 5
Dependent Claim
23 words
A method according to claim 1 , wherein the known number of bit periods S of the received downstream bit-serial signal is eight.
Claim 6
Dependent Claim
20 words
A method according to claim 1 , further comprising generating the free-running high frequency clock signal with a ring oscillator.
Claim 7
Dependent Claim
47 words
A method according to claim 5 , wherein the step of generating the free-running high frequency clock signal with a ring oscillator further comprises generating an even number of signals V having a period of the free-running high frequency clock signal and the phase shifted of 360°/V.
Claim 8
Dependent Claim
16 words
A method according to claim 6 , wherein the even number of signals V is eight.
Claim 9
Dependent Claim
17 words
A method according to claim 1 , wherein the method is implemented in an integrated circuit module.
Claim 10
Dependent Claim
18 words
A method according to claim 8 , wherein the integrated circuit module is positioned on a smart card.
Claim 11
Dependent Claim
39 words
A method according to claim 1 , wherein the local clock signal is phase locked with the downstream bit serial signal at least once every seven bit periods of the downstream bit serial signal by the use of bit-stuffing.
Claim 12
Dependent Claim
40 words
A method according to claim 1 , wherein the counting step is performed during a period of time when the downstream bit serial signal comprises a Sync byte and a PID byte of a USB Token Packet and Data Packet.
Claim 13
Dependent Claim
32 words
A method according to claim 3 , wherein the known received downstream bit serial pattern is within a Sync byte and a PID byte of a USB Token Packet and Data Packet.
Claim 14
Dependent Claim
19 words
A method according to claim 1 , further comprising a step for determining if T is within predefined limits.
Claim 15
Dependent Claim
33 words
A method according to claim 1 , wherein the local clock signal is used to sample the USB received downstream serial bit data and to time the USB transmitted upstream serial bit data.
Claim 16
Independent Claim
154 words
A device containing a circuit for generating a local clock signal using Universal Serial Bus downstream signals DP and DM, comprising; a) means for receiving the USB downstream differential signals DP and DM and generating a downstream bit-serial signal from the USB downstream signals; b) means for counting a number of cycles R of a free-running high frequency clock signal contained within a known number of bit periods S of the received downstream bit-serial signal; c) means for dividing the counted number of cycles R of the free-running high frequency clock signal by the known number of bit periods S of the received downstream bit-serial signal for determining a resultant number of the free-running high frequency clock cycles T contained within a single bit period of the received downstream bit-serial signal; and d) means for generating a local clock signal having a period equal to the number of free-running high frequency clock cycles T.
Claim 17
Independent Claim
154 words
A device containing a circuit for generating a local clock signal using Universal Serial Bus downstream signals DP and DM, comprising; a) means for receiving the USB downstream differential signals DP and DM and generating a downstream bit-serial signal from the USB downstream signals; b) means for counting a number of cycles R of a free-running high frequency clock signal contained within a known number of bit periods S of the received downstream bit-serial signal; c) means for dividing the counted number of cycles R of the free-running high frequency clock signal by the known number of bit periods S of the received downstream bit-serial signal for determining a resultant number of the free-running high frequency clock cycles T contained within a single bit period of the received downstream bit-serial signal; and d) means for generating a local clock signal having a period equal to the number of free-running high frequency clock cycles T.
Claim 18
Dependent Claim
75 words
A device according to claim 15 wherein the means for generating the local clock signal comprises: a) means for counting the number of the free-running high frequency clock cycles T to generate a period of the local clock signal; and b) means for initializing the counting step when there is a data toggling in the received downstream bit serial signal for locking in phase the generated local clock with the received downstream bit serial signal.
Claim 19
Dependent Claim
38 words
A device according to claim 15 , wherein the means for generating the local clock signal further comprises means for updating the period of the local clock signal when a known received downstream bit serial pattern is recognized.
Claim 20
Dependent Claim
23 words
A device according to claim 15 , wherein the known number of bit periods S of the received downstream bit-serial signal is eight.
Claim 21
Dependent Claim
22 words
A device according to claim 15 , wherein the means for generating the free-running high frequency clock signal is a ring oscillator.
Claim 22
Dependent Claim
49 words
A device according to claim 19 , wherein the means for generating the free-running high frequency clock signal with a ring oscillator further comprises means for generating an even number of signals V having a period of the free-running high frequency clock signal and the phase shifted of 360°/V.
Claim 23
Dependent Claim
16 words
A device according to claim 20 , wherein the even number of signals V is eight.
Claim 24
Dependent Claim
17 words
A device according to claim 15 , wherein the circuit is implemented in an integrated circuit module.
Claim 25
Dependent Claim
18 words
A device according to claim 22 , wherein the integrated circuit module is positioned on a smart card.
Claim 26
Dependent Claim
39 words
A device according to claim 15 , wherein the local clock signal is phase locked with the downstream bit serial signal at least once every seven bit periods of the downstream bit serial signal by the use of bit-stuffing.
Claim 27
Dependent Claim
41 words
A device according to claim 15 , wherein the counting means is performed during a period of time when the downstream bit serial signal comprises a Sync byte and a PID Setup byte of a USB Token Packet and Data Packet.
Claim 28
Dependent Claim
32 words
A device according to claim 17 , wherein the known received downstream bit serial pattern is within a Sync byte and a PID byte of a USB Token Packet and Data Packet.
Claim 29
Dependent Claim
19 words
A device according to claim 15 , further comprising a means for determining if T is within predefined limits.
Claim 30
Dependent Claim
33 words
A device according to claim 15 , wherein the local clock signal is used to sample the USB received downstream serial bit data and to time the USB transmitted upstream serial bit data.
Claim 31
Independent Claim
168 words
A device containing a circuit for generating a local clock signal using Universal Serial Bus downstream signals DP and DM, comprising: a) a differential receiver for receiving the USB downstream differential signals DP and DM and generating a downstream bit-serial signal from the USB downstream signals; b) a first counter connected to the bit serial signal for counting a number of cycles R of a free-running high frequency clock signal contained within a known number of bit periods S of the received downstream bit-serial signal; c) a divider circuit for dividing the counted number of cycles R of the free-running high frequency clock signal by the known number of bit periods S of the received downstream bit-serial signal for determining a resultant number of the free-running high frequency clock cycles T contained within a single bit period of the received downstream bit-serial signal; and d) a second counter for generating a local clock signal having a period equal to the number of free-running high frequency clock cycles T.
Claim 32
Independent Claim
168 words
A device containing a circuit for generating a local clock signal using Universal Serial Bus downstream signals DP and DM, comprising: a) a differential receiver for receiving the USB downstream differential signals DP and DM and generating a downstream bit-serial signal from the USB downstream signals; b) a first counter connected to the bit serial signal for counting a number of cycles R of a free-running high frequency clock signal contained within a known number of bit periods S of the received downstream bit-serial signal; c) a divider circuit for dividing the counted number of cycles R of the free-running high frequency clock signal by the known number of bit periods S of the received downstream bit-serial signal for determining a resultant number of the free-running high frequency clock cycles T contained within a single bit period of the received downstream bit-serial signal; and d) a second counter for generating a local clock signal having a period equal to the number of free-running high frequency clock cycles T.
Claim 33
Dependent Claim
23 words
A device according to claim 29 , wherein the second counter is initialized by data toggling in the received downstream bit serial signal.
Claim 34
Dependent Claim
22 words
A device according to claim 29 , wherein the free-running high frequency clock signal is generated by an eight phase ring oscillator.
Claim 35
Dependent Claim
40 words
A device according to claim 29 , wherein the first counter is enabled during a period of time when the downstream bit serial signal comprises a Sync byte and a PID byte of a USB Token Packet and Data Packet.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2005-01-28 | 2005-07-30 | 2006-01-29 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2009-01-28 | 2009-07-30 | 2010-01-29 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2013-01-28 | 2013-07-30 | 2014-01-29 | $7700.00 | Window Closed / Lapsed |