US6061802A
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Software based clock synchronization
Assignee: GlobalFoundries Inc
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Filing: 1998-07-02
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Granted: 2000-05-09
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Expires: 2018-07-02
Abstract
Abstract A master isochronous clock structure in which the frame-rate clocks of a plurality of data buses are synchronized to a master clock signal. The master clock signal may be derived from the existing clock signals within the computer system or from data received from an external source. The master clock signal may also be used by an operating system scheduler to schedule task that generate or consume blocks of isochronous data. In an alternative embodiment, the drift of a device clock signal relative to a master clock signal is measured and used to synchronize the device clock signal. For example, a mechanism may monitor the level of data in a data buffer. The level of data in the data buffer is a measure of the drift between the clock generating the data and the clock consuming the data. Based upon the level of data in the buffer, synchronization information is provided to synchronize the rates of the clock signals that generate and consume the data. In one embodiment, the level of data in a data buffer is used to synchronize the clock of a video camera. In another embodiment, the level of data in a data buffer is used to synchronize a clock of a telephony codec.
Inventors
- 👤 Dale E. Gulick
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-03 21:12
CPC Classifications
H; H04; H04L; H04L12/00; H04L12/28; H04L12/40; H04L12/40052; H04L12/40058; G; G06; G06F; G06F1/00; G06F1/04; G06F1/12; G06F1/14; G06F5/00; G06F5/06; H04L12/40123
Claims Analysis
Total Claims: 19
Claim 1
Independent Claim
127 words
A computer system comprising: a central processing unit (CPU) including a software program operating on said CPU; a first data bus coupled to said CPU and configured to receive data from a first isochronous device at a first clock rate; a second data bus coupled to said CPU and configured to receive data from a second isochronous device at a second clock rate; a third data bus coupled to said CPU and configured to transfer data at a third clock rate; wherein said software is configured to select said first clock rate or said second clock rate as a master clock rate and output a master clock signal to said third data bus, such that said third clock rate is substantially equal to said master clock rate.
Claim 2
Dependent Claim
127 words
A computer system comprising: a central processing unit (CPU) including a software program operating on said CPU; a first data bus coupled to said CPU and configured to receive data from a first isochronous device at a first clock rate; a second data bus coupled to said CPU and configured to receive data from a second isochronous device at a second clock rate; a third data bus coupled to said CPU and configured to transfer data at a third clock rate; wherein said software is configured to select said first clock rate or said second clock rate as a master clock rate and output a master clock signal to said third data bus, such that said third clock rate is substantially equal to said master clock rate.
Claim 3
Dependent Claim
14 words
The computer system of claim 1 wherein said clock rates are frame clock rates.
Claim 4
Dependent Claim
22 words
The computer system of claim 2 wherein said third clock rate is substantially equal to a multiple of said master clock rate.
Claim 5
Dependent Claim
22 words
The computer system of claim 2 wherein said third clock rate is substantially equal to a divisor of said master clock rate.
Claim 6
Dependent Claim
33 words
The computer system of claim 2 wherein said master clock signal is provided to an interrupt controller of said CPU and said software schedules tasks based on an output of said interrupt controller.
Claim 7
Dependent Claim
23 words
The computer system of claim 5 wherein said interrupt controller includes a divider that divides said master clock signal to generate an interrupt.
Claim 8
Dependent Claim
23 words
The computer system of claim 6 wherein said divider is a programmable divider that divides said master clock signal by a programmed amount.
Claim 9
Dependent Claim
18 words
The computer system of claim 2 wherein said third clock rate is synchronized with said master clock rate.
Claim 10
Dependent Claim
41 words
The computer system of claim 2 further comprising a signal processor coupled between said third data bus and said CPU, wherein said signal processor is configured to interpolate said data of said third data bus to match said master clock rate.
Claim 11
Dependent Claim
58 words
The computer system of claim 2 wherein a first signal processor is coupled between said first data bus and said CPU and a second signal processor is coupled between said second data bus and said CPU, wherein said software is configured to interpolate data of a data bus which is not selected to generate said master clock rate.
Claim 12
Independent Claim
65 words
A method of synchronizing multiple clocks within a computer system, comprising: receiving a first data signal at a first clock rate; receiving a second data signal at a second clock rate; a software program selecting either said first clock rate or said second clock rate as a master clock rate; synchronizing a third clock rate of a third data signal to said master clock rate.
Claim 13
Independent Claim
65 words
A method of synchronizing multiple clocks within a computer system, comprising: receiving a first data signal at a first clock rate; receiving a second data signal at a second clock rate; a software program selecting either said first clock rate or said second clock rate as a master clock rate; synchronizing a third clock rate of a third data signal to said master clock rate.
Claim 14
Dependent Claim
13 words
The method of claim 11 wherein said clock rates are frame clock rates.
Claim 15
Dependent Claim
21 words
The method of claim 12 wherein said third clock rate is substantially equal to a multiple of said master clock rate.
Claim 16
Dependent Claim
21 words
The method of claim 12 wherein said third clock rate is substantially equal to a divisor of said master clock rate.
Claim 17
Dependent Claim
32 words
The method of claim 12 further comprising conveying a master clock signal to an interrupt controller of said CPU and said software scheduling tasks based on an output of said interrupt controller.
Claim 18
Dependent Claim
17 words
The method of claim 12 wherein said third clock rate is synchronized with said master clock rate.
Claim 19
Dependent Claim
23 words
The method of claim 12 wherein a signal processor is configured to interpolate said third data signal to match said master clock rate.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2003-05-09 | 2003-11-08 | 2004-05-09 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2007-05-09 | 2007-11-08 | 2008-05-09 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2011-05-09 | 2011-11-08 | 2012-05-09 | $7700.00 | Window Closed / Lapsed |