US5870441A
Expired / Lapsed
US
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Distributed clocking system
Assignee: IPC Systems Inc
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Filing: 1997-08-25
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Granted: 1999-02-09
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Expires: 2017-08-25
Abstract
Abstract A clocking mechanism with improved fault tolerance for synchronizing a distributed processing system includes a plurality of distributed clock sources. Each clock source may operate as a master clock for synchronizing the operations of the entire system or as a slave to an external clock while remaining available, in a backup capacity, to operate as a master clock in the event of a failure in the previous master clock. A clock selection mechanism is provided in each distributed switch element for selecting the best clock available to each switch element for synchronization. A failure recovery mechanism is provided with fast and automatic recovery in the event of a failure in a master clock. A data extraction mechanism is also provided capable of sampling a bit stream that is not phase-aligned, even in the presence of timing jitter and pulse width distortion, and having provisions for detecting a bit slip.
Inventors
- 👤 John M. Cotton
- 👤 Nicholas Necula
- 👤 Bidyut Parruck
- 👤 Fryderyk Tyra
- 👤 Alex T. Wissink
- 👤 Enrique Abreu
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-04 00:14
CPC Classifications
H; H04; H04J; H04J3/00; H04J3/02; H04J3/06; H04J3/0635; H04J3/0685; H04J3/0688; G; G06; G06F; G06F1/00; G06F1/04; G06F1/08; H04J3/0691; H04L; H04L7/00; H04L7/02; H04L7/033; H04L7/0337
Claims Analysis
Total Claims: 22
Claim 1
Independent Claim
66 words
A system for data extraction, comprising: means for selecting a highest ranked clock signal from a plurality of clock signals; means for receiving a digital data signal; means for obtaining a plurality of samples of said digital data signal during each bit duration using said highest ranked clock signal; and means for evaluating said samples to determine a value to be assigned to said each bit.
Claim 2
Independent Claim
66 words
A system for data extraction, comprising: means for selecting a highest ranked clock signal from a plurality of clock signals; means for receiving a digital data signal; means for obtaining a plurality of samples of said digital data signal during each bit duration using said highest ranked clock signal; and means for evaluating said samples to determine a value to be assigned to said each bit.
Claim 3
Dependent Claim
27 words
A system for data extraction according to claim 1, further comprising means for generating multi-phase clock signals having one phase for each of said plurality of samples.
Claim 4
Dependent Claim
45 words
A system for data extraction according to claim 2, wherein said means for obtaining the plurality of samples of said digital data signals further comprises a plurality of flip-flops that each sample said digital data signal on a different phase of said multi-phase clock signals.
Claim 5
Dependent Claim
34 words
A system for data extraction according to claim 1, further comprising means for storing the history of whether said digital data signal is sampled in the beginning or ending portion of a sampled bit.
Claim 6
Dependent Claim
39 words
A system for data extraction according to claim 4, wherein said means for evaluating further comprises means for receiving said history of whether said digital data signal is sampled in the beginning or ending portion of the sampled bit.
Claim 7
Dependent Claim
45 words
A system for data extraction according to claim 5, wherein said means for evaluating assigns a data value based on said plurality of samples and said history of whether said digital data signal is sampled in the beginning or ending portion of the sampled bit.
Claim 8
Independent Claim
124 words
A system for detecting a bit slip, comprising: means for obtaining a plurality of samples of a digital data signal using a highest ranked clock signal selected from a plurality of clock signals; means for storing the history of whether said digital data signal is sampled in the beginning or ending portion of a sampled bit; means for storing an indication of when a bit transition occurs in the middle of said plurality of samples; and means for evaluating said history of whether said digital data signal is sampled in the beginning or ending portion of the sampled bit and said indication of when the bit transition occurs in the middle of said plurality of samples to detect the occurrence of a slipped bit.
Claim 9
Independent Claim
124 words
A system for detecting a bit slip, comprising: means for obtaining a plurality of samples of a digital data signal using a highest ranked clock signal selected from a plurality of clock signals; means for storing the history of whether said digital data signal is sampled in the beginning or ending portion of a sampled bit; means for storing an indication of when a bit transition occurs in the middle of said plurality of samples; and means for evaluating said history of whether said digital data signal is sampled in the beginning or ending portion of the sampled bit and said indication of when the bit transition occurs in the middle of said plurality of samples to detect the occurrence of a slipped bit.
Claim 10
Dependent Claim
39 words
A system for detecting the bit slip according to claim 7, wherein said means for storing the history of whether said digital data signal is sampled in the beginning or ending portion of the sampled bit is a flip-flop.
Claim 11
Dependent Claim
35 words
A system for detecting the bit slip according to claim 7, wherein said means for storing the indication of when the bit transition occurs in the middle of said plurality of samples is a flip-flop.
Claim 12
Dependent Claim
78 words
A system for detecting the bit slip according to claim 7, wherein said means for evaluating detects the occurrence of the slipped bit whenever the history of whether said digital data signal is sampled in the beginning or ending portion of the sampled bit indicates that the sampling is changing from the beginning portion of the bit to the ending portion of the bit and when the bit transition occurs in the middle of said plurality of samples.
Claim 13
Independent Claim
60 words
A method for extracting data, comprising the steps of: selecting a highest ranked clock signal from a plurality of clock signals; receiving a digital data signal; obtaining a plurality of samples of said digital data signal during each bit duration using said highest ranked clock signal; evaluating said samples to determine a value to be assigned to said each bit.
Claim 14
Independent Claim
60 words
A method for extracting data, comprising the steps of: selecting a highest ranked clock signal from a plurality of clock signals; receiving a digital data signal; obtaining a plurality of samples of said digital data signal during each bit duration using said highest ranked clock signal; evaluating said samples to determine a value to be assigned to said each bit.
Claim 15
Dependent Claim
38 words
A method for extracting data according to claim 11, wherein said step of selecting the highest ranked clock signal further includes the step of generating multi-phase clock signals having one phase for each of said plurality of samples.
Claim 16
Dependent Claim
49 words
A method for extracting data according to claim 12, wherein said step of obtaining the plurality of samples of said digital data signal further includes the step of sampling said digital data signal on a different phase of said multi-phase clock signals by means of a plurality of flip-flops.
Claim 17
Dependent Claim
35 words
A method for extracting data according to claim 11, further including the step of storing the history of whether said digital data signal is sampled in the beginning or ending portion of a sampled bit.
Claim 18
Dependent Claim
40 words
A method for extracting data according to claim 14, wherein said step of evaluating further includes the step of receiving said history of whether said digital data signal is sampled in the beginning or ending portion of the sampled bit.
Claim 19
Dependent Claim
50 words
A method for extracting data according to claim 15, wherein said step of evaluating further includes the step of assigning a data value based on said plurality of samples and said history of whether said digital data signal is sampled in the beginning or ending portion of the sampled bit.
Claim 20
Independent Claim
116 words
A method for detecting a bit slip, comprising: obtaining a plurality of samples of a digital data signal using a highest ranked clock signal selected from a plurality of clock signals; storing the history of whether said digital data signal is sampled in the beginning or ending portion of a sampled bit; storing an indication of when a bit transition occurs in the middle of said plurality of samples; and evaluating said history of whether said digital data signal is sampled in the beginning or ending portion of the sampled bit and said indication of when the bit transition occurs in the middle of said plurality of samples to detect the occurrence of a slipped bit.
Claim 21
Independent Claim
116 words
A method for detecting a bit slip, comprising: obtaining a plurality of samples of a digital data signal using a highest ranked clock signal selected from a plurality of clock signals; storing the history of whether said digital data signal is sampled in the beginning or ending portion of a sampled bit; storing an indication of when a bit transition occurs in the middle of said plurality of samples; and evaluating said history of whether said digital data signal is sampled in the beginning or ending portion of the sampled bit and said indication of when the bit transition occurs in the middle of said plurality of samples to detect the occurrence of a slipped bit.
Claim 22
Dependent Claim
81 words
A method for detecting the bit slip according to claim 17, wherein said step of evaluating detects the occurrence of the slipped bit whenever the history of whether said digital data signal is sampled in the beginning or ending portion of the sampled bit indicates that the digital data signal sample is changing from the beginning portion of the bit to the ending portion of the bit and when the bit transition occurs in the middle of said plurality of samples.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2002-02-08 | 2002-08-10 | 2003-02-09 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2006-02-08 | 2006-08-10 | 2007-02-09 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2010-02-08 | 2010-08-10 | 2011-02-09 | $7700.00 | Window Closed / Lapsed |