Self-correcting serial baud/bit alignment

Claim 1

In a serial data communications system wherein a data record is transmitted as a serial data stream from a transmitting device through a communications medium to a receiving device which includes a universal asynchronous/synchronous receiver/transmitter (USART) unit that receives said serial data stream and change it into a parallel data stream and change it into a parallel data stream and forward said data to a subsystem of said receiving device, a circuit arrangement positioned in said USART for synchronizing said receiver to the bit cell boundaries of received data streams comprising: a first circuit means for generating clock pulses with a predetermined frequency; a second circuit means responsive to the clock pulses for aligning said clock pulses with the serial data record and outputting pulses D R ; delay means for delaying D R and generating pulses B R ; a third circuit means for correlating D R and B R and outputting a control signal; a synchronizing latch means having an input signal terminal, a clocked terminal coupled to the first circuit means, a positive and a negative output; and a fourth circuit means having an output coupled to the signal terminal, a first input coupled to the third circuit means and a second input coupled to the negative output of the synchronizing latch means.