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US6330184B1
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Method of operating a semiconductor device
Assignee: NXP USA Inc
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Filing: 2000-09-11
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Granted: 2001-12-11
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Expires: 2020-09-11
Abstract
Abstract A method of operating a semiconductor device that includes a first memory cell with discontinuous storage elements or dots ( 108 ) in lieu of a conventional floating gate can be programmed to at least one of three different states. The different states are possible because the read current for the memory cell is different when the dots are programmed near the source region or near the drain region. Embodiments may use two different potentials for power supplies or three different potentials. The two-potential embodiment simplifies the design, whereas the three-potential embodiment has a reduced risk of disturb problems in adjacent unselected memory cells ( 100 B, 100 C, and 100 D).
Inventors
- 👤 Bruce E. White
- 👤 Bo Jiang
- 👤 Ramachandran Muralidhar
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 02:45
CPC Classifications
G; G11; G11C; G11C16/00; G11C16/02; G11C16/04; G11C16/0466; G11C16/0475; G11C11/00; G11C11/56; G11C11/5621; G11C11/5628; G11C11/5671; G11C16/0408; G11C16/0441; G11C16/0458; G11C16/06; G11C16/10; H; H10; H10D; H10D30/00; H10D30/60; H10D30/68; H10D30/687; G11C16/34; G11C16/3418
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
239 words
A method of operating a semiconductor device including a first memory cell, the method comprising: providing the semiconductor device, wherein a first memory cell has discontinuous storage elements; and programming the first memory cell to a first state, which is one of at least three different states, wherein programming is performed using a first potential and a second potential, wherein a difference between the first and second potentials is no greater than approximately 5 volts; and programming further includes: biasing the first current carrying electrode and the control electrode to the first potential; and biasing the second current carrying electrode and the substrate to the second potential; and wherein the first memory cell includes: a substrate; a first current carrying electrode within the substrate; a second current carrying electrode within the substrate and spaced apart from the first current carrying electrode; a first dielectric layer having a first side and a second side that is opposite the first side, wherein the substrate lies along the first side of the first dielectric layer and the discontinuous storage elements lie along the second side of the first dielectric layer; a second dielectric layer having a first side and a second side that is opposite the first side, wherein the first dielectric layer and the discontinuous storage elements lie along the first side of the second dielectric layer; and a control electrode lies along the second side of the second dielectric layer.
Claim 2
Independent Claim
239 words
A method of operating a semiconductor device including a first memory cell, the method comprising: providing the semiconductor device, wherein a first memory cell has discontinuous storage elements; and programming the first memory cell to a first state, which is one of at least three different states, wherein programming is performed using a first potential and a second potential, wherein a difference between the first and second potentials is no greater than approximately 5 volts; and programming further includes: biasing the first current carrying electrode and the control electrode to the first potential; and biasing the second current carrying electrode and the substrate to the second potential; and wherein the first memory cell includes: a substrate; a first current carrying electrode within the substrate; a second current carrying electrode within the substrate and spaced apart from the first current carrying electrode; a first dielectric layer having a first side and a second side that is opposite the first side, wherein the substrate lies along the first side of the first dielectric layer and the discontinuous storage elements lie along the second side of the first dielectric layer; a second dielectric layer having a first side and a second side that is opposite the first side, wherein the first dielectric layer and the discontinuous storage elements lie along the first side of the second dielectric layer; and a control electrode lies along the second side of the second dielectric layer.
Claim 3
Dependent Claim
47 words
The method of claim 1 , further comprising reprogramming the first memory cell to a second state, wherein programming further includes: biasing the first current carrying electrode, the second current carrying electrode, and substrate to the first potential; and biasing the control electrode to the second potential.
Claim 4
Dependent Claim
47 words
The method of claim 2 , further comprising reprogramming the first memory cell to a third state, wherein programming further includes: biasing the first current carrying electrode, the second current carrying electrode, and substrate to the second potential; and biasing the control electrode to the first potential.
Claim 5
Independent Claim
64 words
A method of operating a semiconductor device including a first memory cell, the method comprising: providing the semiconductor device, wherein a first memory cell has discontinuous storage elements; and programming the first memory cell to a first state, which is one of at least three different states; and wherein an average spacing between the discontinuous storage elements is no less than approximately three nanometers.
Claim 6
Independent Claim
64 words
A method of operating a semiconductor device including a first memory cell, the method comprising: providing the semiconductor device, wherein a first memory cell has discontinuous storage elements; and programming the first memory cell to a first state, which is one of at least three different states; and wherein an average spacing between the discontinuous storage elements is no less than approximately three nanometers.
Claim 7
Independent Claim
57 words
A method of operating a semiconductor device including a first memory cell, comprising: providing the semiconductor device, wherein the first memory cell has discontinuous storage elements, a source region and a drain region; and programming a first portion of the discontinuous storage elements, wherein the first portion is proximal to the source region or the drain region.
Claim 8
Independent Claim
57 words
A method of operating a semiconductor device including a first memory cell, comprising: providing the semiconductor device, wherein the first memory cell has discontinuous storage elements, a source region and a drain region; and programming a first portion of the discontinuous storage elements, wherein the first portion is proximal to the source region or the drain region.
Claim 9
Dependent Claim
20 words
The method of claim 5 , wherein the discontinuous storage elements in the first portion are adjacent to each other.
Claim 10
Dependent Claim
21 words
The method of claim 5 , wherein the first portion further comprises 30 to 50 percent of the discontinuous storage elements.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2004-12-10 | 2005-06-11 | 2005-12-11 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2008-12-10 | 2009-06-11 | 2009-12-11 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2012-12-10 | 2013-06-11 | 2013-12-11 | $7700.00 | Window Closed / Lapsed |