US6326282B1
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method of forming trench isolation in a semiconductor device and structure formed thereby
Assignee: Samsung Electronics Co Ltd
•
Filing: 1999-04-14
•
Granted: 2001-12-04
•
Expires: 2019-04-14
Abstract
Abstract A method of forming trench isolation which protects a nitride liner in the trench during subsequent plasma processing, by forming a high temperature oxide layer, such as an HTO oxide layer or LP-TEOS oxide layer. A trench mask is formed on a semiconductor substrate to define a trench forming region, the semiconductor substrate is etched using the trench mask to form a trench, a thermal oxide layer is formed on a bottom and sidewalls of the trench to remove substrate damage caused by the etching, a material layer is formed on the thermal oxide layer to prevent the bottom and sidewalls of the trench from being oxidized, a protection layer is formed on the oxidation barrier layer, the bottom and sidewalls of the trench are plasma processed, and the trench is then filled with a trench fill material uniformly with respect to the bottom and sidewalls.
Inventors
- 👤 Young-woo Park
- 👤 Yong-chul Oh
- 👤 Won-seong Lee
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 22:41
CPC Classifications
H; H10; H10W; H10W10/00; H10W10/01; H10W10/011; H10W10/014; H10P; H10P14/00; H10P14/60; H10P14/63; H10P14/6302; H10P14/6304; H10P14/6306; H10P14/6326; H10P14/6328; H10P14/6334; H10P14/65; H10P14/6516; H10P14/6529; H10P14/6532; H10P14/69; H10P14/694; H10P14/6943; H10P14/69433; H10W10/0145; H10W10/10; H10W10/17
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
164 words
A method of forming trench isolation in a semiconductor device comprising: forming a trench mask on a semiconductor substrate to define a trench forming region; etching said semiconductor substrate using said trench mask to form a trench therein; forming a thermal oxide layer on a bottom and sidewalls of said trench, said thermal oxide layer removing substrate damage caused by said etching of said semiconductor substrate; forming an oxidation barrier layer on said thermal oxide layer, said oxidation barrier layer preventing said bottom and sidewalls of said trench from being oxidized; forming a protection layer that is resistant to plasma on said oxidation barrier layer; plasma processing said bottom and sidewalls of said trench; and filling up said trench with a trench fill material uniformly with respect to said bottom and sidewalls of said trench, said protection layer comprising an oxide layer selected from a group consisting of an HTO oxide layer and an LP-TEOS oxide layer, formed by deposition techniques at high temperature.
Claim 2
Independent Claim
164 words
A method of forming trench isolation in a semiconductor device comprising: forming a trench mask on a semiconductor substrate to define a trench forming region; etching said semiconductor substrate using said trench mask to form a trench therein; forming a thermal oxide layer on a bottom and sidewalls of said trench, said thermal oxide layer removing substrate damage caused by said etching of said semiconductor substrate; forming an oxidation barrier layer on said thermal oxide layer, said oxidation barrier layer preventing said bottom and sidewalls of said trench from being oxidized; forming a protection layer that is resistant to plasma on said oxidation barrier layer; plasma processing said bottom and sidewalls of said trench; and filling up said trench with a trench fill material uniformly with respect to said bottom and sidewalls of said trench, said protection layer comprising an oxide layer selected from a group consisting of an HTO oxide layer and an LP-TEOS oxide layer, formed by deposition techniques at high temperature.
Claim 3
Dependent Claim
18 words
The method according to claim 1 , wherein said oxidation barrier layer comprises an LPCVD silicon nitride layer.
Claim 4
Dependent Claim
33 words
The method according to claim 2 , wherein said silicon nitride layer comprises a silicon-rich nitride layer having greater silicon content as respectively compared to other component contents of the silicon-rich nitride layer.
Claim 5
Dependent Claim
21 words
The method according to claim 1 , wherein said protection layer has a thickness of about 10 Å to 1,000 Å.
Claim 6
Dependent Claim
29 words
The method according to claim 1 , further comprising, after said filling up said trench with said trench fill material, annealing so as to density said trench fill material.
Claim 7
Dependent Claim
25 words
The method according to claim 5 , wherein said annealing is carried out at a temperature of at least 900° C. in N 2 atmosphere.
Claim 8
Dependent Claim
25 words
The method according to claim 5 , wherein said annealing is carried out at a temperature of at least 700° C. in a wet atmosphere.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2004-12-03 | 2005-06-04 | 2005-12-04 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2008-12-03 | 2009-06-04 | 2009-12-04 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2012-12-03 | 2013-06-04 | 2013-12-04 | $7700.00 | Window Closed / Lapsed |