Patent US6324670B1 successfully refreshed from Google Patents.
US6324670B1
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Checksum generator with minimum overflow
Assignee: Micro Focus Software Inc
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Filing: 1999-03-24
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Granted: 2001-11-27
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Expires: 2019-03-24
Abstract
Abstract A checksum generator includes at least one adding circuit for processing a segment of a given message. Associated with the adding circuit is a register for temporarily holding the partial sum that is being calculated by the adding circuit. The register is configured to hold a partial sum that is larger than the message segments being added by the adding circuit. The partial sums can thus expand into the register, eliminating the creation of a carry bit that must be added back in during each add cycle. After the last message segment has been processed, the adding circuit preferably adds the high order portion of the register to the low order portion and adds back any carry bit generated thereby to produce a checksum value that may be loaded into the given message.
Inventors
- 👤 Dana M. Henriksen
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-07 12:28
CPC Classifications
H; H03; H03M; H03M13/00; H03M13/03; H03M13/05; H03M13/09; H03M13/091
Claims Analysis
Total Claims: 23
Claim 1
Independent Claim
106 words
A checksum generator for calculating a checksum value for a given message, the checksum generator comprising: at least one adder having first and second inputs, a sum output and a carry-bit return, the first input configured to receive a plurality of message segments, each message segment being n-bits in length; and at least one register coupled to the sum output to temporarily store a partial sum from the at least one adder, and to the second input to return its contents to the at least one adder, the register configured so as to be greater in size than the n-bit message segments received by the adder.
Claim 2
Dependent Claim
106 words
A checksum generator for calculating a checksum value for a given message, the checksum generator comprising: at least one adder having first and second inputs, a sum output and a carry-bit return, the first input configured to receive a plurality of message segments, each message segment being n-bits in length; and at least one register coupled to the sum output to temporarily store a partial sum from the at least one adder, and to the second input to return its contents to the at least one adder, the register configured so as to be greater in size than the n-bit message segments received by the adder.
Claim 3
Dependent Claim
56 words
The checksum generator of claim 1 wherein the at least one adder performs an add operation on each received message segment and the register contents to generate a corresponding partial sum, and further wherein the corresponding partial sum is stored at the register such that the add operation is free from creating from a carry bit.
Claim 4
Dependent Claim
54 words
The checksum generator of claim 2 wherein the register is apportioned into two sections and the at least one adder, in response to processing a last message segment, performs an add operation on the partial sum of the two register sections and adds back any carry bit created thereby to generate the checksum value.
Claim 5
Dependent Claim
19 words
The checksum generator of claim 3 wherein the checksum value is temporarily stored at one of the register sections.
Claim 6
Dependent Claim
16 words
The checksum generator of claim 4 wherein the size of the register is 2 times n.
Claim 7
Dependent Claim
27 words
The checksum generator of claim 4 wherein each message segment is 16-bits, the size of the register is 32-bits and the two register sections are each 16-bits.
Claim 8
Dependent Claim
16 words
The checksum generator of claim 1 wherein the size of the register is 2 times n.
Claim 9
Dependent Claim
38 words
The checksum generator of claim 1 wherein each message segment is one of 16-bits and 32-bits, the size of the register is one of 32-bits and 64-bits, and the two register sections are one of 16-bits and 32-bits.
Claim 10
Dependent Claim
129 words
A checksum generator for calculating a checksum value for a given message, the checksum generator comprising: two or more adders each having first and second inputs and a sum output, at least one adder having a carry-bit return, the first input of each adder configured to receive a plurality of message segments, each being n-bits in length; and at least one register apportioned into two or more sections each coupled to the sum output of a respective adder to temporarily store a partial sum from the respective adder, each register section coupled to the second input of its respective adder to return its contents to the respective adder, each register section configured to be greater in size than the n-bit message segments received by the two or more adders.
Claim 11
Dependent Claim
129 words
A checksum generator for calculating a checksum value for a given message, the checksum generator comprising: two or more adders each having first and second inputs and a sum output, at least one adder having a carry-bit return, the first input of each adder configured to receive a plurality of message segments, each being n-bits in length; and at least one register apportioned into two or more sections each coupled to the sum output of a respective adder to temporarily store a partial sum from the respective adder, each register section coupled to the second input of its respective adder to return its contents to the respective adder, each register section configured to be greater in size than the n-bit message segments received by the two or more adders.
Claim 12
Dependent Claim
67 words
The checksum generator of claim 9 wherein each adder performs an add operation on each received message segment and the contents of its respective register section in parallel to generate a corresponding partial sum, and further wherein the corresponding partial sum from each adder is stored at its respective register section such that the add operation for each adder is free from creating from a carry bit.
Claim 13
Dependent Claim
45 words
The checksum generator of claim 10 wherein, in response to processing a last message segment, one adder performs an add with carry operation on the partial sum in each of the register sections to generate a result that is placed in a first register section.
Claim 14
Dependent Claim
46 words
The checksum generator of claim 11 wherein the first register section is apportioned into first and second portions and further wherein one adder performs an add operation on the first and second portions and adds back any carry bit created thereby to generate the checksum value.
Claim 15
Dependent Claim
30 words
The checksum generator of claim 12 wherein the size of each register section is 2 times n and the two portions of the first register are each ½ times n.
Claim 16
Dependent Claim
32 words
The checksum generator of claim 12 wherein each message segment is 16-bits, the size of each register section is 32-bits and the two portions of the first register section are each 16-bits.
Claim 17
Independent Claim
218 words
A method for generating a checksum value for a given message split into one or more message streams, each message stream corresponding to a plurality of message segments each having a length of n-bits, the method comprising the steps of: configuring at least one data register into one or more sections for temporarily storing a partial sum, each register section having a size that is greater than n-bits; associating each of the one or more message streams with a selected register section; summing each message segment from the respective message streams with its associated register section to create a partial sum; placing the partial sums for each message stream in its associated register section such that the summing step is free from creating carry bits due to the one or more register sections being greater than n-bits in size; in response to summing last message segments in each message stream, adding the one or more register sections to create a first intermediate sum; placing the first intermediate sum in a first register section; apportioning the first register section into first and second register portions; adding the first and second register portions to create a second intermediate sum and a first carry value; and adding the second intermediate sum and the first carry value to obtain the checksum value.
Claim 18
Independent Claim
218 words
A method for generating a checksum value for a given message split into one or more message streams, each message stream corresponding to a plurality of message segments each having a length of n-bits, the method comprising the steps of: configuring at least one data register into one or more sections for temporarily storing a partial sum, each register section having a size that is greater than n-bits; associating each of the one or more message streams with a selected register section; summing each message segment from the respective message streams with its associated register section to create a partial sum; placing the partial sums for each message stream in its associated register section such that the summing step is free from creating carry bits due to the one or more register sections being greater than n-bits in size; in response to summing last message segments in each message stream, adding the one or more register sections to create a first intermediate sum; placing the first intermediate sum in a first register section; apportioning the first register section into first and second register portions; adding the first and second register portions to create a second intermediate sum and a first carry value; and adding the second intermediate sum and the first carry value to obtain the checksum value.
Claim 19
Dependent Claim
24 words
The method of claim 15 wherein the step of summing the message segments from the one or more message streams is performed in parallel.
Claim 20
Dependent Claim
25 words
The method of claim 16 further comprising the step of configuring each message segment to have a size equal to ½ its respective register section.
Claim 21
Dependent Claim
39 words
The method of claim 17 wherein the message segments are each 16-bits, the at least one register is 64-bits in size, the register sections are 32-bits in size and the first and second register portions are 16-bits in size.
Claim 22
Dependent Claim
19 words
The method of claim 18 further comprising the step of appending the calculated checksum value to the given message.
Claim 23
Dependent Claim
42 words
The method of claim 15 wherein the step of adding the one or more register sections further creates a second carry value and the method further comprises the step of adding back in the second carry value to the first intermediate sum.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2004-11-26 | 2005-05-28 | 2005-11-27 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2008-11-26 | 2009-05-28 | 2009-11-27 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2012-11-26 | 2013-05-28 | 2013-11-27 | $7700.00 | Window Closed / Lapsed |