Checksum generation circuit and method

Claim 2

A checksum generator circuit comprising: a first adder having first and second adder inputs, a first sum output, and having a first carry-out coupled to feedback a first generated carry bit to a carry-in of the first adder, said first adder input being coupled to receive first input data, and said first sum output being coupled to feedback first partial sum data to said second adder input; and a second adder having third and fourth adder inputs, a second sum output, and having a second carry-out coupled to feedback a second generated carry bit to a carry-in of the second adder, said second sum output being coupled to feedback second partial sum data to said third adder input, and wherein said fourth adder input is coupled to said first adder to selectively receive second input data, said first partial sum data from said first sum output, and said first generated carry bit from said first carry-out.

Claim 3

A checksum generator as claimed in claim 1, including a first register coupled from said first sum output to said second adder input to temporarily store said first partial sum data, and a second register coupled from said second sum output to said third adder input to temporarily store said second partial sum data.

Claim 4

A checksum generator as claimed in claim 2, including a multiplexer having an output coupled to said fourth adder input and having inputs coupled to said first sum output, said first carry-out and to a data source to receive said second input data.

Claim 5

A checksum generator as claimed in claim 3, wherein said multiplexer is coupled to said first carry-out by way of a carry register for temporarily storing said first generated carry bit.

Claim 6

A checksum generator as claimed in claim 4, including a pre-load circuit coupled to at least one of said first and second registers for initializing said at least one register with previously stored partial sum data.

Claim 7

A checksum generator for generating an N bit checksum from data provided on first and second N bit data inputs, comprising: a first adder for summing two N bit operands, an output of the first adder being coupled to feedback an N bit sum result to a first input of the first adder, a carry-out of the first adder being coupled to feedback a carry bit to a carry-in of the first adder, and a second input of the first adder being coupled to receive data from said first N bit data input; and a second adder for summing two N bit operands, an output of the second adder being coupled to feedback an N bit sum result to a first input of the second adder, a carry-out of the second adder being coupled to feedback a carry bit to a carry-in of the second adder, and a second input of the second adder being coupled to receive data from said second N bit data input; wherein the output of the second adder and the carry-out of the second adder are multiplexed with said first N bit data input to the second input of the first adder.

Claim 8

A checksum generator for generating an N bit checksum from data provided on first and second N bit data inputs, comprising: a first adder for summing two N bit operands, an output of the first adder being coupled to feedback an N bit sum result to a first input of the first adder, a carry-out of the first adder being coupled to feedback a carry bit to a carry-in of the first adder, and a second input of the first adder being coupled to receive data from said first N bit data input; and a second adder for summing two N bit operands, an output of the second adder being coupled to feedback an N bit sum result to a first input of the second adder, a carry-out of the second adder being coupled to feedback a carry bit to a carry-in of the second adder, and a second input of the second adder being coupled to receive data from said second N bit data input; wherein the output of the second adder and the carry-out of the second adder are multiplexed with said first N bit data input to the second input of the first adder.

Claim 9

A checksum generator as claimed in claim 6, including a first result register coupled to said output of said first adder and said first input of said first adder, and a second result register coupled to said output of said second adder and said first input of said second adder.

Claim 10

A checksum generator as claimed in claim 7, including a first multiplexer having inputs coupled to receive said first N bit data input, said output of said second adder, said carry-out of said second adder, and a zero input, and having an output coupled to said second input of said first adder.

Claim 11

A checksum generator as claimed in claim 8, including a carry register coupled to said store a carry-out value from said carry-out of said second adder and to pass the stored carry-out value to said multiplexer.

Claim 12

A checksum generator as claimed in claim 9, including a second multiplexer having an output coupled to said first result register, and having a first input coupled to said output of said first adder, and at least one second input coupled to receive initialization data.

Claim 13

A checksum generator as claimed in claim 10, including a third multiplexer having an output coupled to said second result register, and having a first input coupled to said output of said second adder, and a second input coupled to receive initialization data.

Claim 14

A checksum generator as claimed in claim 11, wherein said first and second N bit data inputs each comprise a 16 bit data input.

Claim 15

A checksum generator circuit for generating a checksum from a stream of data values, comprising: a first binary adder having first and second adder inputs, a first sum output, a first carry-output and a first carry input, said first carry-output being coupled to said first carry input; a second binary adder having third and fourth adder inputs, a second sum output, a second carry-output and a second carry input, said second carry-output being coupled to said second carry input; a first register coupled to said first sum output and said first adder input; a second register coupled to said second sum output and said third adder input; and a multiplexer having an output coupled to said second adder input, and having inputs coupled to receive a first data input, and coupled to said second register and said second carry-output; said fourth adder input being coupled to receive a second data input.

Claim 16

A checksum generator circuit for generating a checksum from a stream of data values, comprising: a first binary adder having first and second adder inputs, a first sum output, a first carry-output and a first carry input, said first carry-output being coupled to said first carry input; a second binary adder having third and fourth adder inputs, a second sum output, a second carry-output and a second carry input, said second carry-output being coupled to said second carry input; a first register coupled to said first sum output and said first adder input; a second register coupled to said second sum output and said third adder input; and a multiplexer having an output coupled to said second adder input, and having inputs coupled to receive a first data input, and coupled to said second register and said second carry-output; said fourth adder input being coupled to receive a second data input.

Claim 17

A checksum generator circuit as claimed in claim 13, wherein said first and second data inputs comprises 16 bit data words, and said first and second sum outputs comprise 16 bit outputs.

Claim 18

A checksum generator circuit as claimed in claim 13, further comprising an initialization multiplexer having an output coupled to said first register, a first input coupled to said first sum output and at least one second input coupled to receive initialization data for initializing said first register.

Claim 19

A checksum generator circuit as claimed in claim 15, further comprising a second initialization multiplexer having an output coupled to said second register, a first input coupled to said second sum output and a second input coupled to receive a binary zero input.

Claim 22

A method as claimed in claim 17, wherein said first and second data streams each comprise streams of 16-bit data, and said checksum comprises a 16-bit sum.

Claim 23

A method as claimed in claim 17, including a step of summing at least one of said first and second data streams with an initial partial sum.

Claim 24

A method as claimed in claim 19, including a step of suspending the summing of said first and second data streams, and storing at least one partial sum.

Claim 25

A data transmission interface for coupling a host computer for communication through an asynchronous transfer mode (ATM) telecommunications network, comprising: a load engine coupled to retrieve a packet of data from said host computer; a segmentation engine for segmenting said data packet into cells and passing the cells of data to said ATM network; and a checksum generator coupled to receive said data packet from said load engine, and for generating a checksum value from said data packet to be passed to said ATM network by way of said segmentation engine, said checksum generator comprising: a first adder having first and second adder inputs, a first sum output, and having a first carry-out coupled to feedback a first generated carry bit to a carry-in of the first adder, said first adder input being coupled to receive first input data from said load engine, and said first sum output being coupled to feedback first partial sum data to said second adder input; and a second adder having third and fourth adder inputs, a second sum output, and having a second carry-out coupled to feedback a second generated carry bit to a carry-in of the second adder, said second sum output being coupled to feedback second partial sum data to said third adder input, and wherein said fourth adder input is coupled to said first adder to selectively receive second input data from said load engine, said first partial sum data from said first sum output, and said first generated carry bit from said first carry-out.

Claim 26

A data transmission interface for coupling a host computer for communication through an asynchronous transfer mode (ATM) telecommunications network, comprising: a load engine coupled to retrieve a packet of data from said host computer; a segmentation engine for segmenting said data packet into cells and passing the cells of data to said ATM network; and a checksum generator coupled to receive said data packet from said load engine, and for generating a checksum value from said data packet to be passed to said ATM network by way of said segmentation engine, said checksum generator comprising: a first adder having first and second adder inputs, a first sum output, and having a first carry-out coupled to feedback a first generated carry bit to a carry-in of the first adder, said first adder input being coupled to receive first input data from said load engine, and said first sum output being coupled to feedback first partial sum data to said second adder input; and a second adder having third and fourth adder inputs, a second sum output, and having a second carry-out coupled to feedback a second generated carry bit to a carry-in of the second adder, said second sum output being coupled to feedback second partial sum data to said third adder input, and wherein said fourth adder input is coupled to said first adder to selectively receive second input data from said load engine, said first partial sum data from said first sum output, and said first generated carry bit from said first carry-out.

Claim 27

A data transmission interface as claimed in claim 21, including a transmission buffer memory coupled to said load engine and said segmentation engine for buffering said data packet, said transmission buffer memory also being coupled to receive said checksum value from said second sum output for insertion of said checksum value in a header portion of the data packet buffered in said buffer memory.

Claim 28

A data transmission interface as claimed in claim 22, wherein said data packet is retrieved by said load engine in four-byte words, said first input data comprising a first half of each word of the data packet and said second input data comprising a second half of each word of the data packet.