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US6307659B1
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US
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Optoelectronic transceiver having an adaptable logic level signal detect output
Assignee: Stratos International Inc
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Filing: 1997-09-24
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Granted: 2001-10-23
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Expires: 2017-09-24
Abstract
Abstract An optoelectronic transceiver is provided having an adaptable logic level signal detect output. The preferred embodiments are configured to generate various logic level signal detected signals directly for use by the transceiver host device. A first embodiment generates the SD output based on the actual optical power received over the optical transfer medium. When the received optical power exceeds a predetermined threshold, the monitor voltage exceeds the reference voltage, and the signal detected output is set. The output stage of the circuit can be configured such that in the true state, meaning a signal has been detected, a TTL level signal, a CMOS signal, or a high voltage or high current signal is set to true. The high voltage and high current configurations may be set to any value required under the specific requirements of the application. In a second embodiment an AC signal detecting circuit generates the SD output. A peak signal is compared against an average voltage signal, and when the peak signal exceeds the average signal by a predetermined amount, the SD output is set true. As with the first embodiment, the output stage of the circuit can be configured such that in the true state, meaning a signal has been detected, a TTL level signal, a CMOS signal, or a high voltage or high current signal is set to true. The high voltage and high current configurations may be set to any value required under the specific requirements of the application. Multiple solder pads may be provided on the transceiver printed circuit board such that additional biasing components can be added to the output circuitry. The prearranged solder pads allow the SD output to be adaptable to any logic level that a specific application requires.
Inventors
- 👤 Patrick B. Gilliland
- 👤 Michael F. Leger
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-05 21:07
CPC Classifications
H; H04; H04B; H04B10/00; H04B10/60; H04B10/66; H04B10/69
Claims Analysis
Total Claims: 16
Claim 1
Independent Claim
125 words
A 1×9 optoelectronic transceiver module having a TTL logic level signal detected output, comprising: an SC-duplex receptacle disposed at a first end of the module for connecting to an SC-duplex fiber optic connector; a single array of nine electrical contact pins disposed on a second end of the module; a transmit optical sub-assembly on the module and configured to transmit optical signals over an optical transfer medium; a receive optical sub-assembly on the module and configured to receive an optical signal and convert the optical signal to an electrical signal; a data detect circuit on the module for providing an output signal in response to the electrical signal above a predetermined threshold; and a TTL output driver on the module for driving said output signal.
Claim 2
Dependent Claim
125 words
A 1×9 optoelectronic transceiver module having a TTL logic level signal detected output, comprising: an SC-duplex receptacle disposed at a first end of the module for connecting to an SC-duplex fiber optic connector; a single array of nine electrical contact pins disposed on a second end of the module; a transmit optical sub-assembly on the module and configured to transmit optical signals over an optical transfer medium; a receive optical sub-assembly on the module and configured to receive an optical signal and convert the optical signal to an electrical signal; a data detect circuit on the module for providing an output signal in response to the electrical signal above a predetermined threshold; and a TTL output driver on the module for driving said output signal.
Claim 3
Dependent Claim
38 words
The 1×9 optoelectronic transceiver module of claim 1 wherein the data detect circuit includes a comparator having a first input driven by an output of the receive optical subassembly, and a second input driven by a reference voltage.
Claim 4
Dependent Claim
21 words
The 1×9 optoelectronic transceiver module of claim 2 wherein the TTL output driver includes a transistor and a passive biasing network.
Claim 5
Dependent Claim
35 words
The 1×9 optoelectronic transceiver module of claim 3 wherein the passive biasing network comprises first and second resistors connected in series, the junction between the first and second resistors also connected to the the transistor.
Claim 6
Dependent Claim
135 words
A 1×9 optoelectronic transceiver module having a signal detected output logic level exceeding 5 volts, comprising: an SC-duplex receptacle disposed at a first end of the module for connecting to an SC-duplex fiber optic connector; a single array of nine electrical contact pins disposed on a second end of the module; a transmit optical sub-assembly on the module and configured to transmit optical signals over an optical transfer medium; a receive optical sub-assembly on the module and configured to receive an optical signal and convert the optical signal to an electrical signal; a data detect circuit on the module for providing an output signal in response to the electrical signal above a predetermined threshold; and an output driver capable of driving an output voltage over 5 volts on the module for driving said output signal.
Claim 7
Dependent Claim
135 words
A 1×9 optoelectronic transceiver module having a signal detected output logic level exceeding 5 volts, comprising: an SC-duplex receptacle disposed at a first end of the module for connecting to an SC-duplex fiber optic connector; a single array of nine electrical contact pins disposed on a second end of the module; a transmit optical sub-assembly on the module and configured to transmit optical signals over an optical transfer medium; a receive optical sub-assembly on the module and configured to receive an optical signal and convert the optical signal to an electrical signal; a data detect circuit on the module for providing an output signal in response to the electrical signal above a predetermined threshold; and an output driver capable of driving an output voltage over 5 volts on the module for driving said output signal.
Claim 8
Dependent Claim
37 words
The 1×9 optoelectronic transceiver module of claim 5 wherein the data detect circuit includes a comparator having a first input driven by output of the receive optical subassembly, and a second input driven by a reference voltage.
Claim 9
Dependent Claim
35 words
The 1×9 optoelectronic transceiver module of claim 6 wherein the output driver includes a transistor capable of sustaining an output voltage in excess of 5 volts that is driven by the output of the comparator.
Claim 10
Dependent Claim
18 words
The 1×9 optoelectronic transceiver module of claim 7 wherein the transistor comprises an open collector bi-polar junction transistor.
Claim 11
Dependent Claim
125 words
A 1×9 optoelectronic transceiver module having a CMOS logic level signal detected output, comprising: an SC-duplex receptacle disposed at the first end of the module for connecting to an SC-duplex fiber optic connector; a single array of nine electrical contact pins disposed on the second end of the module; a receive optical sub-assembly on the module and configured to receive an optical signal and convert the optical signal to an electrical signal; a transmit optical sub-assembly on the module and configured to transmit optical signals over an optical transfer medium; a data detect circuit on the module for providing an output signal in response to the electrical signal above a predetermined threshold; and a CMOS output driver on the module for driving said output signal.
Claim 12
Dependent Claim
125 words
A 1×9 optoelectronic transceiver module having a CMOS logic level signal detected output, comprising: an SC-duplex receptacle disposed at the first end of the module for connecting to an SC-duplex fiber optic connector; a single array of nine electrical contact pins disposed on the second end of the module; a receive optical sub-assembly on the module and configured to receive an optical signal and convert the optical signal to an electrical signal; a transmit optical sub-assembly on the module and configured to transmit optical signals over an optical transfer medium; a data detect circuit on the module for providing an output signal in response to the electrical signal above a predetermined threshold; and a CMOS output driver on the module for driving said output signal.
Claim 13
Dependent Claim
176 words
A 1×9 optoelectronic transceiver having a selectable logic level signal detected output, comprising: an SC-duplex receptacle disposed at a first end of the module for connecting to an SC-duplex fiber optic connector; a single array of nine electrical contact pins disposed on a second end of the module; a transmit optical sub-assembly on the module and configured to transmit optical signals over an optical transfer medium; a receive optical sub-assembly on the module and configured to receive an optical signal and convert the optical signal to an electrical signal; a data detect circuit on the module for providing an output signal in response to the electrical signal above a predetermined threshold; and an output driver on the module for driving said output signal, said output driver comprising a comparator having an input driven by the data detect circuit, and said output driver further comprising a configurable output signal wherein the logic level of the configurable output signal is established by a selectable biasing network connected to an open collector transistor for providing said configurable output signal.
Claim 14
Dependent Claim
176 words
A 1×9 optoelectronic transceiver having a selectable logic level signal detected output, comprising: an SC-duplex receptacle disposed at a first end of the module for connecting to an SC-duplex fiber optic connector; a single array of nine electrical contact pins disposed on a second end of the module; a transmit optical sub-assembly on the module and configured to transmit optical signals over an optical transfer medium; a receive optical sub-assembly on the module and configured to receive an optical signal and convert the optical signal to an electrical signal; a data detect circuit on the module for providing an output signal in response to the electrical signal above a predetermined threshold; and an output driver on the module for driving said output signal, said output driver comprising a comparator having an input driven by the data detect circuit, and said output driver further comprising a configurable output signal wherein the logic level of the configurable output signal is established by a selectable biasing network connected to an open collector transistor for providing said configurable output signal.
Claim 15
Dependent Claim
109 words
A signal detect output circuit to be placed in a 1×9 optoelectronic transceiver having a selectable logic level signal detect output, comprising: a data detect circuit on the module for providing an output signal in response to the electrical signal above a predetermined threshold; and an output driver on the module for driving said output signal, said output driver comprising a comparator having an input driven by the data detect circuit, and said output driver further comprising a configurable output signal wherein the logic level of the configurable output signal is established by a selectable biasing network connected to an open collector transistor for providing said configurable output signal.
Claim 16
Dependent Claim
109 words
A signal detect output circuit to be placed in a 1×9 optoelectronic transceiver having a selectable logic level signal detect output, comprising: a data detect circuit on the module for providing an output signal in response to the electrical signal above a predetermined threshold; and an output driver on the module for driving said output signal, said output driver comprising a comparator having an input driven by the data detect circuit, and said output driver further comprising a configurable output signal wherein the logic level of the configurable output signal is established by a selectable biasing network connected to an open collector transistor for providing said configurable output signal.
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| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
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| 3.5 Years (Year 4) | 2004-10-22 | 2005-04-23 | 2005-10-23 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2008-10-22 | 2009-04-23 | 2009-10-23 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2012-10-22 | 2013-04-23 | 2013-10-23 | $7700.00 | Window Closed / Lapsed |