Method of fabricating a capacitor under bit line structure for a dynamic random access memory device

Claim 1

A method of fabricating a capacitor under bit line structure, for a dynamic random access memory (DRAM), device, on a semiconductor substrate, comprising the steps of: forming transfer gate transistors on said semiconductor substrate, comprised of gate structures located on an underlying gate insulator layer, with first insulator spacers on the sides of said gate structures, and comprised with source/drain regions located in a region of said semiconductor substrate not covered by said gate structures; forming self-aligned contact (SAC), openings in said first insulator layer, exposing top portions of said source/drain regions; forming conductive plugs in said SAC openings, having a first group of conductive plugs and a second group of conductive plugs; forming capacitor openings in a second insulator layer, exposing the top portion of a first group of conductive plugs to be used for storage node contacts, and forming a bit line contact hole, exposing said second group of conductive plugs to be used as a lower level bit line contact structure; depositing a conductive layer, such as a first polysilicon layer, with said conductive layer covering exposed surfaces of said capacitor openings, and with said first polysilicon layer completely filling said bit line contact hole; removing portions of said conductive layer from the top surface of said second insulator layer, to form storage node structures in said capacitor openings, and to simultaneously form an upper level, bit line contact structure in said bit line contact hole; depositing a capacitor dielectric layer, a second polysilicon layer, and an overlying third insulator layer; performing a patterning procedure in said third insulator layer, in said second polysilicon layer, and in said capacitor dielectric layer, to form a bit line opening, exposing the top surface of said upper level bit line contact structure, and to simultaneously define capacitor structures, comprised of an overlying top electrode structure, said capacitor dielectric layer, and said storage node structure, with said top electrode structure comprised of said second polysilicon layer; forming second insulator spacers on the sides of said bit line opening; and forming a bit line structure in said bit line contact opening.

Claim 2

A method of fabricating a capacitor under bit line structure, for a dynamic random access memory (DRAM), device, on a semiconductor substrate, comprising the steps of: forming transfer gate transistors on said semiconductor substrate, comprised of gate structures located on an underlying gate insulator layer, with first insulator spacers on the sides of said gate structures, and comprised with source/drain regions located in a region of said semiconductor substrate not covered by said gate structures; forming self-aligned contact (SAC), openings in said first insulator layer, exposing top portions of said source/drain regions; forming conductive plugs in said SAC openings, having a first group of conductive plugs and a second group of conductive plugs; forming capacitor openings in a second insulator layer, exposing the top portion of a first group of conductive plugs to be used for storage node contacts, and forming a bit line contact hole, exposing said second group of conductive plugs to be used as a lower level bit line contact structure; depositing a conductive layer, such as a first polysilicon layer, with said conductive layer covering exposed surfaces of said capacitor openings, and with said first polysilicon layer completely filling said bit line contact hole; removing portions of said conductive layer from the top surface of said second insulator layer, to form storage node structures in said capacitor openings, and to simultaneously form an upper level, bit line contact structure in said bit line contact hole; depositing a capacitor dielectric layer, a second polysilicon layer, and an overlying third insulator layer; performing a patterning procedure in said third insulator layer, in said second polysilicon layer, and in said capacitor dielectric layer, to form a bit line opening, exposing the top surface of said upper level bit line contact structure, and to simultaneously define capacitor structures, comprised of an overlying top electrode structure, said capacitor dielectric layer, and said storage node structure, with said top electrode structure comprised of said second polysilicon layer; forming second insulator spacers on the sides of said bit line opening; and forming a bit line structure in said bit line contact opening.

Claim 18

A method of fabricating a capacitor under bit line structure for a dynamic random access memory (DRAM), device, on a semiconductor substrate, featuring simultaneous patterning of storage node structures and a bit line contact structure, and simultaneous definition of capacitor structures and a bit line opening, comprising the steps of: forming transfer gate transistors on said semiconductor substrate, comprised of silicon nitride capped, polycide gate structures located on an underlying silicon dioxide gate insulator layer, with first silicon nitride spacers on the sides of said silicon nitride capped, polycide gate structures, and comprised with source/drain regions located in a region of said semiconductor substrate not covered by said silicon nitride capped, polycide gate structures; depositing a first silicon oxide layer; forming self-aligned contact (SAC), openings in said silicon oxide layer, exposing top portions of said source/drain regions; depositing a first polysilicon layer, completely filing said SAC openings; performing a first chemical mechanical polishing (CMP), procedure to form a first group of storage node contact structures, comprised of said first polysilicon layer, in a first group of SAC openings, and forming a lower level bit line contact structure, comprised of said first polysilicon layer, in a second SAC opening; depositing a second silicon oxide layer; forming capacitor openings in said second silicon oxide layer, exposing the top surface of said storage node contact structures, and forming a narrow diameter, bit line contact hole, exposing a portion of the top surface said lower level bit line contact structure; depositing a second polysilicon layer, coating exposed surfaces of said capacitor opening while completely filling said narrow diameter bit line contact hole; forming a hemispherical grain (HSG), silicon layer on said second polysilicon layer; performing a second CMP procedure removing portions of said HSG silicon layer, and portions of said second polysilicon layer, from the top surface of said second silicon oxide, to simultaneously form said storage node structures in said capacitor openings, and said upper level, bit line contact structure in said narrow bit line contact hole; depositing a capacitor dielectric layer; depositing a third polysilicon layer; depositing a third silicon oxide layer; performing a patterning procedure comprised of removal of exposed portions of said third silicon oxide layer, of said third polysilicon layer, and of said capacitor dielectric layer, forming said bit line opening, exposing the top surface of said upper level bit line contact structure, and simultaneously defining said capacitor structures, comprised of an overlying top electrode structure, defined from said third polysilicon layer, and comprised of said capacitor dielectric layer, and of said storage node structure; forming second silicon nitride spacers on the sides of said bit line opening; depositing a titanium layer; depositing a titanium nitride layer; depositing a tungsten layer completely filling said bit line opening; and patterning of said tungsten layer, of said titanium nitride layer, and of said titanium layer, forming a bit line structure in said bit line contact opening.

Claim 19

A method of fabricating a capacitor under bit line structure for a dynamic random access memory (DRAM), device, on a semiconductor substrate, featuring simultaneous patterning of storage node structures and a bit line contact structure, and simultaneous definition of capacitor structures and a bit line opening, comprising the steps of: forming transfer gate transistors on said semiconductor substrate, comprised of silicon nitride capped, polycide gate structures located on an underlying silicon dioxide gate insulator layer, with first silicon nitride spacers on the sides of said silicon nitride capped, polycide gate structures, and comprised with source/drain regions located in a region of said semiconductor substrate not covered by said silicon nitride capped, polycide gate structures; depositing a first silicon oxide layer; forming self-aligned contact (SAC), openings in said silicon oxide layer, exposing top portions of said source/drain regions; depositing a first polysilicon layer, completely filing said SAC openings; performing a first chemical mechanical polishing (CMP), procedure to form a first group of storage node contact structures, comprised of said first polysilicon layer, in a first group of SAC openings, and forming a lower level bit line contact structure, comprised of said first polysilicon layer, in a second SAC opening; depositing a second silicon oxide layer; forming capacitor openings in said second silicon oxide layer, exposing the top surface of said storage node contact structures, and forming a narrow diameter, bit line contact hole, exposing a portion of the top surface said lower level bit line contact structure; depositing a second polysilicon layer, coating exposed surfaces of said capacitor opening while completely filling said narrow diameter bit line contact hole; forming a hemispherical grain (HSG), silicon layer on said second polysilicon layer; performing a second CMP procedure removing portions of said HSG silicon layer, and portions of said second polysilicon layer, from the top surface of said second silicon oxide, to simultaneously form said storage node structures in said capacitor openings, and said upper level, bit line contact structure in said narrow bit line contact hole; depositing a capacitor dielectric layer; depositing a third polysilicon layer; depositing a third silicon oxide layer; performing a patterning procedure comprised of removal of exposed portions of said third silicon oxide layer, of said third polysilicon layer, and of said capacitor dielectric layer, forming said bit line opening, exposing the top surface of said upper level bit line contact structure, and simultaneously defining said capacitor structures, comprised of an overlying top electrode structure, defined from said third polysilicon layer, and comprised of said capacitor dielectric layer, and of said storage node structure; forming second silicon nitride spacers on the sides of said bit line opening; depositing a titanium layer; depositing a titanium nitride layer; depositing a tungsten layer completely filling said bit line opening; and patterning of said tungsten layer, of said titanium nitride layer, and of said titanium layer, forming a bit line structure in said bit line contact opening.