Method of fabricating DRAM capacitors

Claim 1

A method for fabricating a semiconductor device, comprising the steps of: providing a semiconductor substrate including at least a transistor which comprises a first spacer around a side wall of the transistor and a first silicon nitride layer over the transistor; forming and patterning a first oxide layer to form a contact window to expose a source region therein on the semiconductor substrate; forming a bit line which couples with the source region on the semiconductor substrate; forming and patterning a second silicon nitride layer to form a second spacer around a side wall of the bit line; forming a third silicon nitride layer on the first oxide layer, the bit line and the second spacer; forming a second oxide layer on the third silicon nitride layer; forming a third oxide layer on the second oxide layer; patterning the third oxide layer, the third silicon nitride layer and the second oxide layer to expose a drain region on the semiconductor substrate; forming a plug which couples with the drain region; patterning the third oxide layer and the second oxide layer, whereby the third oxide layer and the second oxide layer are made to form a cylindrical structure; forming a polysilicon layer on the cylindrical structure and a top surface of the plug; removing the polysilicon layer on the cylindrical structure and the top surface of the plug about to expose the cylindrical structure; removing the exposed cylindrical structure, whereby the polysilicon layer formes a bottom electrode; forming a dielectric layer on the bottom electrode; and forming a top electrode on the dielectric layer.

Claim 2

A method for fabricating a semiconductor device, comprising the steps of: providing a semiconductor substrate including at least a transistor which comprises a first spacer around a side wall of the transistor and a first silicon nitride layer over the transistor; forming and patterning a first oxide layer to form a contact window to expose a source region therein on the semiconductor substrate; forming a bit line which couples with the source region on the semiconductor substrate; forming and patterning a second silicon nitride layer to form a second spacer around a side wall of the bit line; forming a third silicon nitride layer on the first oxide layer, the bit line and the second spacer; forming a second oxide layer on the third silicon nitride layer; forming a third oxide layer on the second oxide layer; patterning the third oxide layer, the third silicon nitride layer and the second oxide layer to expose a drain region on the semiconductor substrate; forming a plug which couples with the drain region; patterning the third oxide layer and the second oxide layer, whereby the third oxide layer and the second oxide layer are made to form a cylindrical structure; forming a polysilicon layer on the cylindrical structure and a top surface of the plug; removing the polysilicon layer on the cylindrical structure and the top surface of the plug about to expose the cylindrical structure; removing the exposed cylindrical structure, whereby the polysilicon layer formes a bottom electrode; forming a dielectric layer on the bottom electrode; and forming a top electrode on the dielectric layer.