Method for manufacturing DRAM cell with fork-shaped capacitor

Claim 1

A method for manufacturing a forked-shape capacitor as part of a Dynamic Random Access Memory cell, comprising: (a) providing a partially completed silicon integrated circuit structure further comprising a plurality of Field Effect Transistors, each having source, drain, and gate regions, the electrode contacting said gate region having the shape of a hollow rectangle with an interior, one side contacting said gate region and the parallel side on a layer of field oxide, adjacent to said gate region and separated from it by said source region; (b) then coating the structure with a first layer of silicon oxide which is then selectively removed so that it does not cover the interior of said gate electrode; (c) then coating the structure with a first layer of doped polycrystalline silicon and with a second layer of silicon oxide; (d) then selectively removing that part of said second layer of silicon oxide that overlies the interior of said gate; (e) then conformally coating the entire structure with a third layer of silicon oxide; (f) then anisotropically etching said third layer of silicon oxide down to the level of said first layer of polycrystalline silicon, thereby leaving said second layer of silicon oxide unaltered, and thereby forming spacers that extend inwards from the vertical walls of said second layer of silicon oxide, partially covering the exposed portion of said first layer of polycrystalline silicon; (g) then etching said first layer of polycrystalline silicon down to the level of the upper surface of said gate electrode; (h) then removing said second layer of silicon oxide, including said spacers; (i) then selectively removing all of said first layer of polycrystalline silicon except the part that overlies the interior of said gate and overlaps said first layer of silicon oxide, thereby forming said first layer of polycrystalline silicon into a bottom electrode; (j) then coating said bottom electrode with a layer of a capacitor dielectric; and (k) then coating said capacitor dielectric layer with a second layer of polycrystalline silicon, thereby forming a top electrode.

Claim 2

A method for manufacturing a forked-shape capacitor as part of a Dynamic Random Access Memory cell, comprising: (a) providing a partially completed silicon integrated circuit structure further comprising a plurality of Field Effect Transistors, each having source, drain, and gate regions, the electrode contacting said gate region having the shape of a hollow rectangle with an interior, one side contacting said gate region and the parallel side on a layer of field oxide, adjacent to said gate region and separated from it by said source region; (b) then coating the structure with a first layer of silicon oxide which is then selectively removed so that it does not cover the interior of said gate electrode; (c) then coating the structure with a first layer of doped polycrystalline silicon and with a second layer of silicon oxide; (d) then selectively removing that part of said second layer of silicon oxide that overlies the interior of said gate; (e) then conformally coating the entire structure with a third layer of silicon oxide; (f) then anisotropically etching said third layer of silicon oxide down to the level of said first layer of polycrystalline silicon, thereby leaving said second layer of silicon oxide unaltered, and thereby forming spacers that extend inwards from the vertical walls of said second layer of silicon oxide, partially covering the exposed portion of said first layer of polycrystalline silicon; (g) then etching said first layer of polycrystalline silicon down to the level of the upper surface of said gate electrode; (h) then removing said second layer of silicon oxide, including said spacers; (i) then selectively removing all of said first layer of polycrystalline silicon except the part that overlies the interior of said gate and overlaps said first layer of silicon oxide, thereby forming said first layer of polycrystalline silicon into a bottom electrode; (j) then coating said bottom electrode with a layer of a capacitor dielectric; and (k) then coating said capacitor dielectric layer with a second layer of polycrystalline silicon, thereby forming a top electrode.