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US6286128B1
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Method for design optimization using logical and physical information
Assignee: Synopsys Inc
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Filing: 1998-06-12
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Granted: 2001-09-04
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Expires: 2018-06-12
Abstract
Abstract A method for design optimization using logical and physical information is provided. In one embodiment, a method for design optimization using logical and physical information, includes receiving a behavioral description of an integrated circuit or a portion of an integrated circuit, optimizing placement of circuit elements in accordance with a first cost function, and optimizing logic of the circuit elements in accordance with a second cost function, in which the optimizing placement of the circuit elements and the optimizing logic of the circuit elements are performed concurrently. The method can further include optimizing routing in accordance with a third cost function, in which the optimizing routing, the optimizing placement of the circuit elements, and the optimizing logic of the circuit elements are performed concurrently.
Inventors
- 👤 Lawrence Pileggi
- 👤 Majid Sarrafzadeh
- 👤 Sharad Malik
- 👤 Abhijeet Chakraborty
- 👤 Archie Li
- 👤 Robert Eugene Shortt
- 👤 Christopher Dunn
- 👤 David Gluss
- 👤 Dennis Yamamoto
- 👤 Dinesh Gaitonde
- 👤 Douglas B. Boyle
- 👤 Emre Tuncer
- 👤 Eric McCaughrin
- 👤 Feroze Peshotan Taraporevala
- 👤 Gary K. Yeap
- 👤 James S. Koford
- 👤 Joseph T. Rahmeh
- 👤 Lilly Shieh
- 👤 Salil R. Raje
- 👤 Sam Jung Kim
- 👤 Satamurthy Pullela
- 👤 Yau-Tsun Steven Li
- 👤 Tong Gao
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-07 19:12
CPC Classifications
G; G06; G06F; G06F30/00; G06F30/30; G06F30/32; G06F30/327; G06F30/39; G06F30/398; G06F2119/00; G06F2119/06
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
46 words
A method for design optimization using logical and physical information, comprising: receiving a behavioral description of an integrated circuit; synthesizing, from said behavioral description, circuit elements of said integrated circuit; and concurrently optimizing placement and logic of said circuit elements in accordance with a cost function.
Claim 2
Independent Claim
46 words
A method for design optimization using logical and physical information, comprising: receiving a behavioral description of an integrated circuit; synthesizing, from said behavioral description, circuit elements of said integrated circuit; and concurrently optimizing placement and logic of said circuit elements in accordance with a cost function.
Claim 3
Dependent Claim
20 words
The method of claim 1 , wherein said concurrently optimizing further comprising: optimizing routing in accordance with said cost function.
Claim 4
Dependent Claim
30 words
The method of claim 1 , wherein logic of said circuit elements is optimized using techniques including one or more of gate sizing, pin assignment, logic replication, cloning, and buffering.
Claim 5
Dependent Claim
19 words
The method of claim 1 , wherein said cost function takes into account delays and slacks between circuit elements.
Claim 6
Dependent Claim
16 words
The method of claim 1 , wherein said concurrently optimizing introduces virtual buffers between circuit elements.
Claim 7
Dependent Claim
18 words
The method of claim 1 , wherein said cost function takes into account wire density between circuit elements.
Claim 8
Independent Claim
104 words
A method for design optimization using logical and physical information, comprising: receiving a behavioral description of an integrated circuit; synthesizing, from said behavioral description, circuit elements of said integrated circuit; and concurrently optimizing placement and logic of said circuit elements in accordance with a cost function, said concurrently optimizing comprising: executing an inner loop, the inner loop comprising optimizing placement of the circuit elements, reversing any logic changes that did not result in a change in the placement of the circuit elements, and optimizing logic of the circuit elements; and executing an outer loop, the outer loop comprising executing a performance driven global router.
Claim 9
Independent Claim
104 words
A method for design optimization using logical and physical information, comprising: receiving a behavioral description of an integrated circuit; synthesizing, from said behavioral description, circuit elements of said integrated circuit; and concurrently optimizing placement and logic of said circuit elements in accordance with a cost function, said concurrently optimizing comprising: executing an inner loop, the inner loop comprising optimizing placement of the circuit elements, reversing any logic changes that did not result in a change in the placement of the circuit elements, and optimizing logic of the circuit elements; and executing an outer loop, the outer loop comprising executing a performance driven global router.
Claim 10
Dependent Claim
26 words
The method of claim 7 , further comprising: executing a final placement of the circuit elements; and executing a global router to perform a final routing.
Claim 11
Dependent Claim
32 words
The method of claim 7 further comprising: clustering said circuit elements into topological clusters; and partitioning an area corresponding to a semiconductor substrate of the integrated circuit based on the topological clusters.
Claim 12
Dependent Claim
36 words
The method of claim 7 , further comprising: repeating the inner loop if the optimizing logic changes the circuit elements; and repeating the outer loop if the optimizing placement changes the placement of the circuit elements.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2004-09-03 | 2005-03-05 | 2005-09-04 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2008-09-03 | 2009-03-05 | 2009-09-04 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2012-09-03 | 2013-03-05 | 2013-09-04 | $7700.00 | Window Closed / Lapsed |