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US6286116B1
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Built-in test method for content addressable memories
Assignee: Hewlett Packard Development Co LP
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Filing: 1999-03-26
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Granted: 2001-09-04
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Expires: 2019-03-26
Abstract
Abstract A method and apparatus for built in self test, BIST, of content addressable memory, CAM, and associated random access memory, RAM, is described. The method and apparatus may most beneficially be used for difficult to test situations such as embedded CAM or other memory types. There are no external memory read operations to determine the contents of a memory location, so little additional circuitry or overhead, such as separate read ports, is required on the embedded memory for implementation of the BIST. Only a number generator, a shift register and an OR gate with inputs from each of the CAM word match lines are added to the circuit in which the memory is embedded. The test uses a set of unique data patterns, each one spaced from the others by two bit locations, a walking inversion test, and a complement and reverse pattern test to determine what type of error and the error location. With such a system the testing of embedded CAM or other memory types such as RAM and FIFO is simplified, and the test fault coverage is improved.
Inventors
- 👤 Dilip K. Bhavsar
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 15:41
CPC Classifications
G; G11; G11C; G11C15/00; G11C29/00; G11C29/04; G11C29/08; G11C29/10; G11C29/12
Claims Analysis
Total Claims: 23
Claim 1
Independent Claim
130 words
A method of built in self testing a content addressable memory, comprising the steps of: creating a set of unique binary data patterns, the number of the patterns being at least as large as the number of words contained in the content addressable memory; writing a different one of the unique patterns into each one of the word locations contained in the content addressable memory; comparing each one of the set of unique patterns with each word location in the content addressable memory; determining with a match indicator whether each one of the compared unique patterns matched the contents of any one of the words contained in the content addressable memory, and indicating an error if any one of the compared patterns indicates no match with any of the words.
Claim 2
Independent Claim
130 words
A method of built in self testing a content addressable memory, comprising the steps of: creating a set of unique binary data patterns, the number of the patterns being at least as large as the number of words contained in the content addressable memory; writing a different one of the unique patterns into each one of the word locations contained in the content addressable memory; comparing each one of the set of unique patterns with each word location in the content addressable memory; determining with a match indicator whether each one of the compared unique patterns matched the contents of any one of the words contained in the content addressable memory, and indicating an error if any one of the compared patterns indicates no match with any of the words.
Claim 3
Dependent Claim
32 words
The method of claim 1 wherein the set of unique binary data patterns each has at least two bit positions that differ in value from any other one of the data patterns.
Claim 4
Dependent Claim
67 words
The method of claim 2 wherein each one of the patterns of the set of unique binary patterns having at least two different bit locations are provided by attaching two copies of one of a second set of unique data patterns having at least one bit location different between members of the set, and having a bit length one half as long as the unique data patterns.
Claim 5
Dependent Claim
78 words
The method of claim 1 wherein the step of determining with a match indicator whether each one of the compared unique patterns matched the contents of any one of the words contained in the content addressable memory, and indicating an error if any one of the compared patterns indicates no match with any of the words further employs an OR gate having as inputs the match lines of each one of the words in the content addressable memory.
Claim 6
Dependent Claim
76 words
The method of claim 1 further comprising: testing an attached random access memory along with testing the content addressable memory, by performing the comparing step twice, first with a write enable signal of the random access memory asserted to copy the content addressable memory data to the attached random access memory; and asserting a read enable signal of the random access memory to rewrite the data into the content addressable memory and repeating the comparing step.
Claim 7
Dependent Claim
21 words
The method of claim 1 wherein the content addressable memory is part of a system to test embedded random access memories.
Claim 8
Dependent Claim
43 words
The method of claim 1 , further comprising: inverting a first bit of the unique patterns and repeating the comparing and determining steps; and indicating an error if any one of the compared patterns does indicate a match with any of the words.
Claim 9
Dependent Claim
43 words
The method of claim 1 , further comprising: repeating the inverting step with each individual one of the bits of the unique patterns until all bits in each unique pattern have been inverted and compared to the contents of the content addressable memory.
Claim 10
Dependent Claim
29 words
The method of claim 1 , further comprising: creating the logical complement of each unique pattern and repeating all previous steps after the writing step using the complement patterns.
Claim 11
Dependent Claim
28 words
The method of claim 1 , further comprising: creating the reverse of each unique pattern and repeating all previous steps after the writing step using the reverse patterns.
Claim 12
Dependent Claim
118 words
Apparatus for testing a content addressable memory, comprising: a pattern generator for creating a set of unique binary data patterns, the number of the patterns being at least as large as the number of words contained in the content addressable memory, the pattern generator writing a different one of the unique patterns into each one of the word locations contained in the content addressable memory; and comparison means responsive to the pattern generator for comparing each one of the set of unique patterns with each word location in the content addressable memory, and for determining whether each one of the compared unique patterns matched the contents of any one of the words contained in the content addressable memory.
Claim 13
Dependent Claim
118 words
Apparatus for testing a content addressable memory, comprising: a pattern generator for creating a set of unique binary data patterns, the number of the patterns being at least as large as the number of words contained in the content addressable memory, the pattern generator writing a different one of the unique patterns into each one of the word locations contained in the content addressable memory; and comparison means responsive to the pattern generator for comparing each one of the set of unique patterns with each word location in the content addressable memory, and for determining whether each one of the compared unique patterns matched the contents of any one of the words contained in the content addressable memory.
Claim 14
Dependent Claim
33 words
Apparatus as claimed in claim 11 , further comprising a walking inversion logic circuit for inverting a first bit of the unique patterns and repeating the comparing and determining by the comparison means.
Claim 15
Dependent Claim
54 words
Apparatus as claimed in claim 12 , wherein the walking inversion logic further repeats the inverting such that each individual one of the bits of the unique patterns is inverted one at a time until all bits in each unique pattern have been inverted and compared to the contents of the content addressable memory.
Claim 16
Dependent Claim
56 words
Apparatus as claimed in claim 13 , further comprising: means for creating the logical complement of each unique pattern, the pattern generator being responsive to the logical compliment patterns by writing different ones of said patterns to each one of the CAM word locations; and the comparison means further compares and determines using the complement patterns.
Claim 17
Dependent Claim
57 words
Apparatus as claimed in claim 14 , the pattern generator comprising; means for creating the reverse of each unique pattern; the pattern generator writing a different one of the reversed unique patterns into each one of the word locations contained in the content addressable memory; and the comparison means further comparing and determining using the reverse patterns.
Claim 18
Dependent Claim
80 words
The apparatus of claim 15 further comprising an attached random access memory which is tested along with the content addressable memory, the comparison means further comparing the unique patterns twice, first with a write enable signal of the random access memory asserted to copy the content addressable memory data to the attached random access memory, then second asserting a read enable signal of the random access memory to rewrite the data into the content addressable memory and repeating the comparing.
Claim 19
Dependent Claim
31 words
The apparatus of claim 15 wherein the comparison means further comprises an OR logic gate whose inputs comprise the match outputs of each of the words in the content addressable memory.
Claim 20
Dependent Claim
18 words
The apparatus of claim 15 wherein the content addressable memory is an embedded memory in an electronic device.
Claim 21
Dependent Claim
28 words
The apparatus of claim 18 wherein the apparatus for testing the content addressable memory is part of the electronic device in which the content addressable memory is embedded.
Claim 22
Independent Claim
165 words
An apparatus for built in self testing of embedded memory, comprising: a unique binary bit pattern generator connected to data inputs and compare inputs of an array of content addressable memory cells; a shift register connected to the pattern generator and the inputs of the array for shifting and reversing the order of the unique data patterns; a random access memory having at least one word storage location attached to each row of the array of content addressable memory cells, for storing and writing the unique binary bit patterns; a logic gate attached to all of the individual rows of the content addressable memory, for determining if a compare input matches the unique binary data pattern in any one of the rows of the array of content addressable memory; and a working output device including: (i) a memory to store, and (ii) an output device to indicate, when a unique data pattern matched one of the unique data patterns stored in the content addressable memory.
Claim 23
Independent Claim
165 words
An apparatus for built in self testing of embedded memory, comprising: a unique binary bit pattern generator connected to data inputs and compare inputs of an array of content addressable memory cells; a shift register connected to the pattern generator and the inputs of the array for shifting and reversing the order of the unique data patterns; a random access memory having at least one word storage location attached to each row of the array of content addressable memory cells, for storing and writing the unique binary bit patterns; a logic gate attached to all of the individual rows of the content addressable memory, for determining if a compare input matches the unique binary data pattern in any one of the rows of the array of content addressable memory; and a working output device including: (i) a memory to store, and (ii) an output device to indicate, when a unique data pattern matched one of the unique data patterns stored in the content addressable memory.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2004-09-03 | 2005-03-05 | 2005-09-04 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2008-09-03 | 2009-03-05 | 2009-09-04 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2012-09-03 | 2013-03-05 | 2013-09-04 | $7700.00 | Window Closed / Lapsed |