US6285725B1
Expired / Lapsed
US
⏱️ 0.0 years remaining
Charge pump circuit
Assignee: SK Hynix Inc
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Filing: 1998-11-18
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Granted: 2001-09-04
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Expires: 2018-11-18
Abstract
Abstract A charge pump circuit in a DLL device used as a clock compensation device is disclosed. A controller for controlling current value and a driver for driving the controller are added to the existing charge pump circuit. Thus, the charge pump circuit reduces lock time and the size of output jitter so that performance of the DLL device can be improved.
Inventors
- 👤 Jun Bae Sung
- 👤 Byeong Yeol Kim
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 19:45
CPC Classifications
H; H03; H03L; H03L7/00; H03L7/06; H03L7/08; H03L7/085; H03L7/089; H03L7/0891; H03L7/0895; H03L7/0896; G; G11; G11C; G11C16/00; G11C16/02; G11C16/06; H03L7/095; H03L7/10; H03L7/107; H03L7/1072; H03L7/0898
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
119 words
A charge pump circuit for obtaining a short lock time and a low jitter comprising: a lock time/jitter control means, connected to a power source supply terminal and a ground terminal of the charge pump circuit, for controlling current value; and a lock time/jitter driving means for outputting a driving signal of the lock time/jitter control means, wherein the lock time/jitter driving means includes: a counter for receiving a phase detector output signal and a charge pump reset signal to prevent the phase detector output signal from becoming unstable; and a lock time/jitter control signal generating means for outputting a control signal of the lock time/jitter control means from an output of the counter and a power source voltage.
Claim 2
Dependent Claim
119 words
A charge pump circuit for obtaining a short lock time and a low jitter comprising: a lock time/jitter control means, connected to a power source supply terminal and a ground terminal of the charge pump circuit, for controlling current value; and a lock time/jitter driving means for outputting a driving signal of the lock time/jitter control means, wherein the lock time/jitter driving means includes: a counter for receiving a phase detector output signal and a charge pump reset signal to prevent the phase detector output signal from becoming unstable; and a lock time/jitter control signal generating means for outputting a control signal of the lock time/jitter control means from an output of the counter and a power source voltage.
Claim 3
Dependent Claim
19 words
The charge pump circuit as claimed in claim 1 , wherein the counter includes a plurality of D flip-flops.
Claim 4
Dependent Claim
22 words
The charge pump circuit as claimed in claim 1 , wherein the lock time/jitter control signal generating means includes a D flip-flop.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2004-09-03 | 2005-03-05 | 2005-09-04 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2008-09-03 | 2009-03-05 | 2009-09-04 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2012-09-03 | 2013-03-05 | 2013-09-04 | $7700.00 | Window Closed / Lapsed |