Fuse circuit and redundant decoder

Claim 2

A fuse circuit comprising: a fuse element having first and second nodes; first and second power nodes; a first control circuit, which receives a first initializing signal generated during a time period for setting a device operating mode, connected between said first power node and said first node of said fuse element; a second control circuit, which receives a second initializing signal generated during said time period for setting a device operating mode, connected between said second power node and said second node of said fuse element; and a latch circuit having an input node connected to said second node of said fuse element to store information thereon.

Claim 3

The fuse circuit as in claim 1 , further comprising a third control circuit, connected between a third power node and said first node of said fuse element, controlling said first and said second control circuits in response to a command.

Claim 4

The fuse circuit as in claim 2 , wherein said command is a plurality of timing signals.

Claim 5

The fuse circuit as in claim 3 , wherein said plurality of timing signals include at least RAS and CAS.

Claim 6

The fuse circuit as in claim 2 , wherein said first control circuit is a first transistor of a first conductivity type and said second control circuit is a second transistor of a second conductivity type different from said first conductivity type.

Claim 7

The fuse circuit as in claim 2 , wherein said third control circuit activates said first control circuit and said second control circuit in this order in response to said command.

Claim 8

A redundant decoder circuit receiving an address for detecting a programmed address comprising: a plurality of address programming circuits corresponding to bits constituting said address, said address programming circuits comprising: a fuse element having first and second nodes; a first control circuit which receives a first initializing signal generated during a time period for setting a device operating mode, connected between said first power node and said first node of said fuse element; a second control circuit which receives a second initializing signal generated during said time period for setting a device operating mode, connected between said second power node and said second node of said fuse element; a latch circuit having an input node connected to said second node of said fuse element to store information thereon; a select circuit selecting between an inverted level or non-inverted level output of said corresponding bit of said address based on said information stored in said latch circuit; and a gate circuit receiving one of said output of said select circuit of each of said plurality of address programming circuits to detect said programmed address.

Claim 9

A redundant decoder circuit receiving an address for detecting a programmed address comprising: a plurality of address programming circuits corresponding to bits constituting said address, said address programming circuits comprising: a fuse element having first and second nodes; a first control circuit which receives a first initializing signal generated during a time period for setting a device operating mode, connected between said first power node and said first node of said fuse element; a second control circuit which receives a second initializing signal generated during said time period for setting a device operating mode, connected between said second power node and said second node of said fuse element; a latch circuit having an input node connected to said second node of said fuse element to store information thereon; a select circuit selecting between an inverted level or non-inverted level output of said corresponding bit of said address based on said information stored in said latch circuit; and a gate circuit receiving one of said output of said select circuit of each of said plurality of address programming circuits to detect said programmed address.

Claim 10

A first circuit comprising: a first voltage supplying circuit, which receives a first initializing signal generated during a time period for setting a device operating mode; a second voltage supplying circuit, which receives a second initializing signal generated during a time period for setting a device operating mode; a fuse connected between said first voltage supplying circuit and said second voltage supplying circuit; and a hold/driver circuit connected to a contact of said first voltage supplying circuit and said fuse; wherein said first voltage supplying circuit provides a first voltage for said contact in conformity with said first initializing signals, said second voltage supplying circuit provides a second voltage for said contact in conformity with said second initializing signal and said hold/driver circuit holds either said first voltage or said second voltage and outputs said first or said second voltage.

Claim 11

A first circuit comprising: a first voltage supplying circuit, which receives a first initializing signal generated during a time period for setting a device operating mode; a second voltage supplying circuit, which receives a second initializing signal generated during a time period for setting a device operating mode; a fuse connected between said first voltage supplying circuit and said second voltage supplying circuit; and a hold/driver circuit connected to a contact of said first voltage supplying circuit and said fuse; wherein said first voltage supplying circuit provides a first voltage for said contact in conformity with said first initializing signals, said second voltage supplying circuit provides a second voltage for said contact in conformity with said second initializing signal and said hold/driver circuit holds either said first voltage or said second voltage and outputs said first or said second voltage.

Claim 12

A fuse circuit as in claim 8 , further comprising a third voltage supplying circuit, connected between a third voltage supplying circuit and said fuse, controlling said first and said second voltage supplying circuits in response to a command.

Claim 13

The fuse circuit as in claim 8 wherein said fuse is cut off or not cut off, a voltage at said contact is fixed or programmed as said first voltage when said fuse is not cut off or as said second voltage when said fuse is cut off.

Claim 14

The fuse circuit as in claim 8 , wherein said first and said second voltage supplying circuits are a plurality of MOS transistors, said hold/driver circuit is several inverters, a composite of a pair of said several inverters is a flip-flop circuit, and said flip-flop circuit holds said first or said second voltage fixed at said contact.