Patent US6281064B1 successfully refreshed from Google Patents.
US6281064B1
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Method for providing dual work function doping and protective insulating cap
Assignee: International Business Machines Corp
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Filing: 1999-06-04
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Granted: 2001-08-28
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Expires: 2019-06-04
Abstract
Abstract A method for providing dual work function doping and borderless array diffusion contacts includes providing a semiconductor substrate, a gate insulator, a conductor on the gate insulator, an insulating cap on the conductor and insulating spacers on sidewalls of a portion of the conductor and the insulating cap. The method also includes doping portions of the semiconductor substrate and the conductor with a first conductive type and other portions with a second conductive type. The conductor may be annealed such that dopants of the first and second conductive types spread over the respective conductors.
Inventors
- 👤 Jack A. Mandelman
- 👤 Gary B. Bronner
- 👤 Ramachandra Divakaruni
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 02:31
CPC Classifications
H; H10; H10B; H10B12/00; H10B12/01; H10B12/09; H10B12/02; H10B12/05; H10D; H10D84/00; H10D84/01; H10D84/0123; H10D84/0126; H10D84/0165; H10D84/0172; H10D84/0177; H10D84/02; H10D84/03; H10D84/038; H10D84/80; H10D84/82; H10D84/83; H10D84/85; H10D84/853
Claims Analysis
Total Claims: 43
Claim 1
Independent Claim
136 words
A method for providing dual work function doping, the method comprising: providing a semiconductor substrate, a gate insulator, a conductor comprising intrinsic polysilicon and overlying silicide layer on said semiconductor substrate and an insulating cap on said conductor; patterning said silicide layer and said insulating cap so as to etch through said silicide layer and said insulating cap while leaving a portion of said intrinsic polysilicon; providing insulating spacers comprising spacer material along sides of said silicide layer and said insulating cap and so as to rest on top of said insic polysilicon; doping first portions of said conductor with a first conductive type dopant and second portions of said conductor with a second conductive type dopant; and annealing said conductor such that dopants of said first and second conductive types spread over said respective conductors.
Claim 2
Independent Claim
136 words
A method for providing dual work function doping, the method comprising: providing a semiconductor substrate, a gate insulator, a conductor comprising intrinsic polysilicon and overlying silicide layer on said semiconductor substrate and an insulating cap on said conductor; patterning said silicide layer and said insulating cap so as to etch through said silicide layer and said insulating cap while leaving a portion of said intrinsic polysilicon; providing insulating spacers comprising spacer material along sides of said silicide layer and said insulating cap and so as to rest on top of said insic polysilicon; doping first portions of said conductor with a first conductive type dopant and second portions of said conductor with a second conductive type dopant; and annealing said conductor such that dopants of said first and second conductive types spread over said respective conductors.
Claim 3
Dependent Claim
33 words
The method of claim 1 , further comprising etching portions of said silicide layer and portions of said insulating cap to form a partial gate conductor stack prior to providing said insulating spacers.
Claim 4
Dependent Claim
74 words
The method of claim 2 , wherein an array region formed in said semiconductor substrate is protected due to predetermined tight spacing of gates in the array region, and a space between adjacent gate conductors are filled with glass, and wherein in a support region of said semiconductor substrate the spacing between gate conductors is larger than in the array region, thereby forming an insulating spacer between adjacent gate conductors in the support region.
Claim 5
Dependent Claim
14 words
The method of claim 1 , wherein said silicide layer comprises WSi x .
Claim 6
Dependent Claim
15 words
The method of claim 1 , wherein said insulating spacers comprise boron silicate glass spacers.
Claim 7
Dependent Claim
27 words
The method of claim 1 , further comprising removing said insulating spacers prior to doping said first and second portions of said semiconductor substrate and said conductor.
Claim 8
Dependent Claim
23 words
The method of claim 1 , wherein said first and second portions of the semiconductor substrate correspond to source and drain contact regions.
Claim 9
Dependent Claim
16 words
The method of claim 7 , wherein said semiconductor substrate includes support regions and array regions.
Claim 10
Dependent Claim
37 words
The method of claim 8 , wherein after annealing the conductor, the method further comprises extending the source and drain regions in said support region of said substrate to a region at least under said annealed conductor.
Claim 11
Dependent Claim
24 words
The method of claim 8 , wherein after annealing said conductor, the method further comprises forming source and drain regions in said array regions.
Claim 12
Dependent Claim
20 words
The method of claim 1 , wherein after annealing said conductor, the method further comprises etching portions of said conductor.
Claim 13
Dependent Claim
19 words
The method of claim 1 , further comprising forming a gate sidewall oxide on sidewalls of said annealed conductor.
Claim 14
Dependent Claim
13 words
An array of gate structures obtained by the method of claim 1 .
Claim 15
Dependent Claim
39 words
The method of claim 1 , wherein an entire conductor gate stack, formed of said intrinsic polysilicon, said silicide layer and said insulating cap and formed prior to said providing of said insulating spacers, is not completely etched through.
Claim 16
Dependent Claim
57 words
The method of claim 1 , wherein a dopant for the conductor is introduced on a horizontal surface in which a support region and the array region of the semiconductor substrate are exposed between the conductor in the array region, and such that ledges on the conductors in the support region of the semiconductor substrate are exposed.
Claim 17
Dependent Claim
38 words
The method of claim 1 , wherein conductors in a support region of the semiconductor substrate are separated such that each gate region is doped independently so that an NFET can be selectively formed adjacent to a PFET.
Claim 18
Dependent Claim
21 words
The method of claim 1 , wherein in an array region of said semiconductor substrate, no separation between the conductors exists.
Claim 19
Independent Claim
126 words
A method for providing dual work function doping, the method comprising: providing a semiconductor substrate, a gate insulator, a conductor comprising intrinsic polysilicon and overlying silicide layer on said semiconductor substrate and an insulating cap on said conductor; providing insulating spacers comprising spacer material along sides of said silicide layer and said insulating cap; doping first portions of said conductor with a first conductive type dopant and second portions of said conductor with a second conductive type dopant; and annealing said conductor such that dopants of said first and second conductive types spread over said respective conductors, wherein after providing the insulating spacers and prior to doping, the method further comprises etching said intrinsic conductor at areas of the conductor not covered by said spacer material.
Claim 20
Independent Claim
126 words
A method for providing dual work function doping, the method comprising: providing a semiconductor substrate, a gate insulator, a conductor comprising intrinsic polysilicon and overlying silicide layer on said semiconductor substrate and an insulating cap on said conductor; providing insulating spacers comprising spacer material along sides of said silicide layer and said insulating cap; doping first portions of said conductor with a first conductive type dopant and second portions of said conductor with a second conductive type dopant; and annealing said conductor such that dopants of said first and second conductive types spread over said respective conductors, wherein after providing the insulating spacers and prior to doping, the method further comprises etching said intrinsic conductor at areas of the conductor not covered by said spacer material.
Claim 21
Dependent Claim
24 words
The method of claim 18 , further comprising forming an oxide layer on portions of the semiconductor substrate not covered with said intrinsic conductor.
Claim 22
Independent Claim
179 words
A method of forming dual work function doping, the method comprising: providing a semiconductor substrate, a gate insulator layer, a relatively undoped polysilicon layer on the semiconductor substrate, a highly conductive silicide layer and an insulating cap on said silicide layer; patterning said silicide and said insulating cap so as to etch through said silicide layer and said insulating cap while leaving a portion of said intrinsic polysilicon; providing insulating spacers comprising spacer material on sidewalls of said insulating cap and said silicide layer and so as to rest on top of said intrinsic polysilicon layer; etching portions of said relatively undoped polysilicon layer which are not covered by the spacer material; removing the spacer material such that said relatively undoped polysilicon layer includes first and second exposed portions; doping first exposed portions of said polysilicon layer with a first conductive type dopant; doping second exposed portions of said polysilicon layer with a second conductive type dopant; and annealing the polysilicon layer such that remaining portions of said polysilicon layer become doped with said first and second conductive types.
Claim 23
Independent Claim
179 words
A method of forming dual work function doping, the method comprising: providing a semiconductor substrate, a gate insulator layer, a relatively undoped polysilicon layer on the semiconductor substrate, a highly conductive silicide layer and an insulating cap on said silicide layer; patterning said silicide and said insulating cap so as to etch through said silicide layer and said insulating cap while leaving a portion of said intrinsic polysilicon; providing insulating spacers comprising spacer material on sidewalls of said insulating cap and said silicide layer and so as to rest on top of said intrinsic polysilicon layer; etching portions of said relatively undoped polysilicon layer which are not covered by the spacer material; removing the spacer material such that said relatively undoped polysilicon layer includes first and second exposed portions; doping first exposed portions of said polysilicon layer with a first conductive type dopant; doping second exposed portions of said polysilicon layer with a second conductive type dopant; and annealing the polysilicon layer such that remaining portions of said polysilicon layer become doped with said first and second conductive types.
Claim 24
Dependent Claim
33 words
The method of claim 20 , further comprising etching portions of said silicide layer and portions of said insulating cap to form a partial gate conductor stack prior to providing said insulating spacers.
Claim 25
Dependent Claim
14 words
The method of claim 20 , wherein said silicide layer comprises WSi x .
Claim 26
Dependent Claim
15 words
The method of claim 20 , wherein said insulating spacers comprise boron silicate glass spacers.
Claim 27
Dependent Claim
36 words
The method of claim 20 , further comprising doping portions of the substrate with said first conductive type prior to annealing said polysilicon layer, said portions of the substrate corresponding to source and drain contact regions.
Claim 28
Dependent Claim
16 words
The method of claim 24 , wherein said semiconductor substrate includes support regions and array regions.
Claim 29
Dependent Claim
32 words
The method of claim 25 , further comprising extending the source and drain contact regions in said substrate region of said substrate to a region at least under said annealed polysilicon layer.
Claim 30
Dependent Claim
25 words
The method of claim 25 , wherein after annealing said polysilicon layer, the method further comprises forming source and drain regions in said array regions.
Claim 31
Dependent Claim
22 words
The method of claim 20 , wherein after annealing said polysilicon layer, the method further comprises etching portions of said polysilicon layer.
Claim 32
Dependent Claim
20 words
The method of claim 20 , further comprising forming a gate sidewall oxide on sidewalls of said annealed polysilicon layer.
Claim 33
Dependent Claim
13 words
An array of gate structures obtained by the method of claim 20 .
Claim 34
Independent Claim
156 words
A method of forming dual work function doping, the method comprising: providing a semiconductor substrate, a gate insulator layer, a relatively undoped polysilicon layer on the semiconductor substrate, a highly conductive silicide layer and an insulating cap on said silicide layer; forming an oxide layer on portions of said semiconductor substrate not covered with said polysilicon layer; providing insulating spacers comprising spacer material on sidewalls of said insulating cap and said silicide layer; etching portions of said relatively undoped polysilicon layer which are not covered by the spacer material; removing the spacer material such that said relatively undoped polysilicon layer includes first and second exposed portions; doping first exposed portions of said polysilicon layer with a first conductive type dopant; doping second exposed portions of said polysilicon layer with a second conductive type dopant; and annealing the polysilicon layer such that remaining portions of said polysilicon layer become doped with said first and second conductive types.
Claim 35
Independent Claim
156 words
A method of forming dual work function doping, the method comprising: providing a semiconductor substrate, a gate insulator layer, a relatively undoped polysilicon layer on the semiconductor substrate, a highly conductive silicide layer and an insulating cap on said silicide layer; forming an oxide layer on portions of said semiconductor substrate not covered with said polysilicon layer; providing insulating spacers comprising spacer material on sidewalls of said insulating cap and said silicide layer; etching portions of said relatively undoped polysilicon layer which are not covered by the spacer material; removing the spacer material such that said relatively undoped polysilicon layer includes first and second exposed portions; doping first exposed portions of said polysilicon layer with a first conductive type dopant; doping second exposed portions of said polysilicon layer with a second conductive type dopant; and annealing the polysilicon layer such that remaining portions of said polysilicon layer become doped with said first and second conductive types.
Claim 36
Independent Claim
89 words
A method for providing dual workfunction doping, the method comprising: providing a semiconductor substrate, a gate insulator over said semiconductor substrate and conductors comprising a deposited semiconductor material over said gate insulator; doping first portions of said semiconductor substrate and first ones of said conductors with a first conductive type dopant and second portions of said semiconductor substrate and second ones of said conductors with a second conductive type dopant; and annealing said conductors such that said first and second dopants spread over said respective first and second conductors.
Claim 37
Independent Claim
89 words
A method for providing dual workfunction doping, the method comprising: providing a semiconductor substrate, a gate insulator over said semiconductor substrate and conductors comprising a deposited semiconductor material over said gate insulator; doping first portions of said semiconductor substrate and first ones of said conductors with a first conductive type dopant and second portions of said semiconductor substrate and second ones of said conductors with a second conductive type dopant; and annealing said conductors such that said first and second dopants spread over said respective first and second conductors.
Claim 38
Independent Claim
154 words
A method for providing dual work function doping, the method comprising: providing a semiconductor substrate, a gate insulator, a conductor comprising intrinsic polysilicon and overlying silicide layer on said semiconductor substrate and an insulating cap on said conductor; patterning said silicide layer and said insulating cap; providing insulating spacers comprising spacer material along sides of said silicide layer and said insulating cap; doping first portions of said conductor with a first conductive type dopant and second portions of said conductor with a second conductive type dopant; and annealing said conductor such that dopants of said first and second conductive types spread over said respective conductors, wherein said intrinsic polysilicon is left unetched during processing of the method, such that said intrinsic polysilicon protects an upper surface of the semiconductor substrate in an array region of said substrate during a doping of a source and a drain in a support region of said semiconductor substrate.
Claim 39
Independent Claim
154 words
A method for providing dual work function doping, the method comprising: providing a semiconductor substrate, a gate insulator, a conductor comprising intrinsic polysilicon and overlying silicide layer on said semiconductor substrate and an insulating cap on said conductor; patterning said silicide layer and said insulating cap; providing insulating spacers comprising spacer material along sides of said silicide layer and said insulating cap; doping first portions of said conductor with a first conductive type dopant and second portions of said conductor with a second conductive type dopant; and annealing said conductor such that dopants of said first and second conductive types spread over said respective conductors, wherein said intrinsic polysilicon is left unetched during processing of the method, such that said intrinsic polysilicon protects an upper surface of the semiconductor substrate in an array region of said substrate during a doping of a source and a drain in a support region of said semiconductor substrate.
Claim 40
Independent Claim
138 words
A method for providing dual work function doping, the method comprising: providing a semiconductor substrate, a gate insulator, a conductor comprising intrinsic polysilicon and overlying silicide layer on said semiconductor substrate and an insulating cap on said conductor; patterning said silicide layer and said insulating cap; providing insulating spacers comprising spacer material along sides of said silicide layer and said insulating cap; doping first portions of said conductor with a first conductive type dopant and second portions of said conductor with a second conductive type dopant; and annealing said conductor such that dopants of said first and second conductive types spread over said respective conductors, wherein a gate stack including said intrinsic polysilicon, said silicide layer and said insulating cap is only partially etched such that etching is performed only through the silicide layer and said insulating cap.
Claim 41
Independent Claim
138 words
A method for providing dual work function doping, the method comprising: providing a semiconductor substrate, a gate insulator, a conductor comprising intrinsic polysilicon and overlying silicide layer on said semiconductor substrate and an insulating cap on said conductor; patterning said silicide layer and said insulating cap; providing insulating spacers comprising spacer material along sides of said silicide layer and said insulating cap; doping first portions of said conductor with a first conductive type dopant and second portions of said conductor with a second conductive type dopant; and annealing said conductor such that dopants of said first and second conductive types spread over said respective conductors, wherein a gate stack including said intrinsic polysilicon, said silicide layer and said insulating cap is only partially etched such that etching is performed only through the silicide layer and said insulating cap.
Claim 42
Independent Claim
150 words
A method for providing dual work function doping, the method comprising: providing a semiconductor substrate, a gate insulator, a conductor comprising intrinsic polysilicon and overlying silicide layer on said semiconductor substrate and an insulating cap on said conductor; patterning said silicide layer and said insulating cap; providing insulating spacers comprising spacer material along sides of said silicide layer and said insulating cap; doping first portions of said conductor with a first conductive type dopant and second portions of said conductor with a second conductive type dopant; and annealing said conductor such that dopants of said first and second conductive types spread over said respective conductors, wherein said insulating spacers are formed only on the sidewall of a gate stack formed by said silicide layer and said insulating cap, and wherein doping occurs only through a horizontal surface of said intrinsic polysilicon and without going through sidewalls of said intrinsic polysilicon.
Claim 43
Independent Claim
150 words
A method for providing dual work function doping, the method comprising: providing a semiconductor substrate, a gate insulator, a conductor comprising intrinsic polysilicon and overlying silicide layer on said semiconductor substrate and an insulating cap on said conductor; patterning said silicide layer and said insulating cap; providing insulating spacers comprising spacer material along sides of said silicide layer and said insulating cap; doping first portions of said conductor with a first conductive type dopant and second portions of said conductor with a second conductive type dopant; and annealing said conductor such that dopants of said first and second conductive types spread over said respective conductors, wherein said insulating spacers are formed only on the sidewall of a gate stack formed by said silicide layer and said insulating cap, and wherein doping occurs only through a horizontal surface of said intrinsic polysilicon and without going through sidewalls of said intrinsic polysilicon.
References Cited (Backward Citations)
US6051494A
Cited
US5937289A
Cited
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| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
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| 3.5 Years (Year 4) | 2004-08-27 | 2005-02-26 | 2005-08-28 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2008-08-27 | 2009-02-26 | 2009-08-28 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2012-08-27 | 2013-02-26 | 2013-08-28 | $7700.00 | Window Closed / Lapsed |