Patent US6281060B1 successfully refreshed from Google Patents.
US6281060B1
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Method of manufacturing a semiconductor device containing a BiCMOS circuit
Assignee: Renesas Semiconductor Manufacturing Co Ltd
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Filing: 1999-02-25
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Granted: 2001-08-28
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Expires: 2019-02-25
Abstract
Abstract A structure of a BiCMOS transistor hindering over-etching of source/drain regions of a MOS transistor and a manufacturing method thereof are provided. A polysilicon film that is to be a gate electrode lower layer of a MOS transistor is formed, and thereon, another polysilicon film that is to be a gate electrode upper layer of the MOS transistor as well as to be a base electrode of a bipolar transistor is formed. Thereafter, etching is conducted to form the polysilicon film to be the base electrode of the bipolar transistor and the gate electrode at the same time. Here, an oxide film shown in FIG. 4 serves as a protective film, thereby hindering over-etching of n type and p type wells to be active regions of respective MOS transistors.
Inventors
- 👤 Takayuki Igarashi
- 👤 Yoshitaka Ohtsu
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-07 21:20
CPC Classifications
H; H10; H10D; H10D84/00; H10D84/01; H10D84/0107; H10D84/0109; H10D84/02; H10D84/03; H10D84/038
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
404 words
A method of manufacturing a semiconductor device provided with a bipolar transistor and a field effect transistor on a semiconductor substrate, comprising the steps of: forming a first conductivity type collector region at least on an underside of a portion that is to become a first active region, the first active region being to be formed from a main surface of the semiconductor substrate to a prescribed depth; forming an element separating insulating film on the main surface of said semiconductor substrate to separately form, on said collector region, said first active region in which said bipolar transistor is to be formed, and, on a region except for said collector region, a second active region of a first conductivity type in which said field effect transistor is to be formed; forming first and second impurity layers of a first conductivity type in said first and second active regions, respectively; forming a first insulating film on the main surface of said second active region; forming a first conductive layer doped with impurity of a first conductivity type on said first insulating layer; forming a first semiconductor layer on the main surface of said first active region and on said first conductive layer; etching said first semiconductor layer, said first conductive layer and said first insulating film to form a layer to be a base electrode on said first active region, and to form a gate electrode consisting of a gate electrode upper layer and a gate electrode lower layer and a gate insulating film on said second active region; introducing a second conductivity type impurity into said layer to be the base electrode to form a base electrode, and introducing a second conductivity type impurity into said second active region to form a first impurity diffusion region; covering with a second insulating film said gate electrode upper layer, said gate electrode lower layer, said gate insulating film, said base electrode, and said first impurity diffusion region; forming an opening in said second insulating film and said base electrode; introducing a second conductivity type impurity from said opening into said first active region to form a second impurity diffusion region to be a base region; forming a sidewall insulating film on a sidewall of said opening; and forming an emitter electrode in contact with said second impurity diffusion region, to be fitted on said sidewall insulating film and an upper surface of said second insulating film.
Claim 2
Independent Claim
404 words
A method of manufacturing a semiconductor device provided with a bipolar transistor and a field effect transistor on a semiconductor substrate, comprising the steps of: forming a first conductivity type collector region at least on an underside of a portion that is to become a first active region, the first active region being to be formed from a main surface of the semiconductor substrate to a prescribed depth; forming an element separating insulating film on the main surface of said semiconductor substrate to separately form, on said collector region, said first active region in which said bipolar transistor is to be formed, and, on a region except for said collector region, a second active region of a first conductivity type in which said field effect transistor is to be formed; forming first and second impurity layers of a first conductivity type in said first and second active regions, respectively; forming a first insulating film on the main surface of said second active region; forming a first conductive layer doped with impurity of a first conductivity type on said first insulating layer; forming a first semiconductor layer on the main surface of said first active region and on said first conductive layer; etching said first semiconductor layer, said first conductive layer and said first insulating film to form a layer to be a base electrode on said first active region, and to form a gate electrode consisting of a gate electrode upper layer and a gate electrode lower layer and a gate insulating film on said second active region; introducing a second conductivity type impurity into said layer to be the base electrode to form a base electrode, and introducing a second conductivity type impurity into said second active region to form a first impurity diffusion region; covering with a second insulating film said gate electrode upper layer, said gate electrode lower layer, said gate insulating film, said base electrode, and said first impurity diffusion region; forming an opening in said second insulating film and said base electrode; introducing a second conductivity type impurity from said opening into said first active region to form a second impurity diffusion region to be a base region; forming a sidewall insulating film on a sidewall of said opening; and forming an emitter electrode in contact with said second impurity diffusion region, to be fitted on said sidewall insulating film and an upper surface of said second insulating film.
Claim 3
Dependent Claim
50 words
The method of manufacturing the semiconductor device according to claim 1 , further comprising the step of: performing salicidation of respective upper portions of said collector region, said base electrode, said emitter electrode, said gate electrode upper layer, and said first impurity diffusion region, to form a metal silicide film.
Claim 4
Dependent Claim
31 words
The method of manufacturing the semiconductor device according to claim 1 , further comprising the step of: forming a metal film on said base electrode and said gate electrode upper layer.
Claim 5
Dependent Claim
62 words
The method of manufacturing the semiconductor device according to claim 1 , further comprising the step of: giving heat treatment to said gate electrode after forming said base electrode and said gate electrode and before forming said first impurity diffusion region, to cause said first conductivity type impurity to diffuse from said gate electrode lower layer to said gate electrode upper layer.
Claim 6
Dependent Claim
68 words
The method of manufacturing the semiconductor device according to claim 1 , wherein said first conductive layer to be the gate electrode lower layer is doped with impurity in concentration of at least 1×10 20 ×{(d 1 +d 2 )/d 2 }cm −3 , wherein d 1 represents film thickness of the gate electrode upper layer and d 2 represents film thickness of the gate electrode lower layer.
Claim 7
Dependent Claim
42 words
The method of manufacturing the semiconductor device according to claim 1 , wherein the film thickness of said gate electrode lower layer has a value equal to the film thickness of said gate electrode minus the film thickness of said base electrode.
Claim 8
Dependent Claim
32 words
The method of manufacturing the semiconductor device according to claim 1 , wherein said field effect transistor consists of a p channel field effect transistor and an n channel field effect transistor.
Claim 9
Dependent Claim
37 words
The method of manufacturing the semiconductor device according to claim 1 , wherein said first conductive layer includes a polysilicon film doped with impurity, and said first semiconductor layer includes a polysilicon film doped with no impurities.
Claim 10
Dependent Claim
72 words
The method of manufacturing the semiconductor device according to claim 1 , wherein said step of forming the emitter electrode comprises the steps of: forming a second semiconductor layer having a layer to be an emitter electrode and a layer to be a resistance element, and etching said second semiconductor layer to form, isolating from each other, said layer to be the emitter electrode and said layer to be the resistance element.
Claim 11
Dependent Claim
77 words
The method of manufacturing the semiconductor device according to claim 9 , further comprising the step of: performing salicidation of respective upper portions of said collector region, said base electrode, said emitter electrode, said gate electrode upper layer, and said first impurity diffusion region to form a metal silicide film, and also performing salicidation of said layer to be the resistance element planarly with a prescribed space to form a metal silicide film for the resistance element.
Claim 12
Dependent Claim
21 words
The method of manufacturing the semiconductor device according to claim 9 , wherein said second semiconductor layer includes a polysilicon film.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2004-08-27 | 2005-02-26 | 2005-08-28 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2008-08-27 | 2009-02-26 | 2009-08-28 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2012-08-27 | 2013-02-26 | 2013-08-28 | $7700.00 | Window Closed / Lapsed |