Semiconductor integrated circuit device

Claim 2

A semiconductor integrated circuit device operating in synchronization with an internal clock signal generated based on an externally input external clock signal, comprising: internal clock signal generation means responsive to said external clock signal for generating a plurality of internal clock signals of different phases; a plurality of internal circuit blocks operating in synchronization with the plurality of internal clock signals generated by said internal clock signal generation means; and a plurality of signal transmission paths provided between said internal clock signal generation means and said plurality of internal circuit blocks, respectively, said plurality of signal transmission paths each transmitting an internal clock signal to a corresponding one of said internal circuit blocks from said internal clock signal generation means and transmitting the internal clock signal transmitted to said internal circuit block to said internal clock signal generation means as a feedback signal, said internal clock signal generation means including phase locked loop means receiving said external clock signal and a first feedback signal among the plurality of feedback signals for synchronizing the phase of a first internal clock signal to be generated with the phase of said external clock signal based on a phase difference between said external clock signal and said first feed back signal, first phase comparison means receiving the first internal clock signal and the first feedback signal corresponding to the first internal clock signal for comparing the phases of these signals to produce a phase difference, second phase comparison means receiving a second internal clock signal among said internal clock signals and a second feedback signal corresponding to the second internal clock signal for comparing the phases of these signals to produce a phase difference, phase difference comparison means for comparing the phase differences produced by said first phase comparison means and said second phase comparison means, and for producing a difference between the phase differences, and delay means receiving and delaying based on the difference produced by said phase difference comparison means said first internal clock signal for generating said second internal clock signal.

Claim 3

A semiconductor integrated circuit device operating in synchronization with an internal clock signal generated based on an externally input external clock signal, comprising: internal clock signal generation means responsive to said external clock signal for generating a plurality of internal clock signals of different phases; a plurality of internal circuit blocks operating in synchronization with the plurality of internal clock signals generated by said internal clock signal generation means; and a plurality of signal transmission paths provided between said internal clock signal generation means and said plurality of internal circuit blocks, respectively, said plurality of signal transmission paths each transmitting an internal clock signal to a corresponding one of said internal circuit block from said internal clock signal generation means and transmitting the internal clock signal transmitted to said internal circuit block to said internal clock signal generation means as a feedback signal, said internal clock signal generation means including first select means receiving said external clock signal and first and second feedback signals among the plurality of feedback signals for selectively outputting a first pair of signals formed of said external clock signal and said first feedback signal and a second pair of signals formed of said first feedback signal and said second feedback signal, phase comparison means receiving the pair of signals of said first select means for comparing the phases of the pair of signals, voltage control oscillation means responsive to the output signal of said phase comparison means for generating a first internal clock signal, delay means delaying the first internal clock signal generated by said voltage control oscillation means for generating a second internal clock signal based on the output signal of said phase comparison means, second select means for selectively applying the output signal of said phase comparison means to said voltage control oscillation means and said delay means; and selective control means for controlling said first and second select means so that the output signal of said second select means is applied to said voltage control oscillation means when said first select means selects said first pair of signals and the output signal of said second select means is applied to said delay means when said first select means selects said second pair of signals.

Claim 4

A semiconductor integrated circuit device operating in synchronization with an internal clock signal generated based on an externally input external clock signal, comprising: internal clock signal generation means responsive to said external clock signal for generating a plurality of internal clock signals of different phases; a plurality of internal circuit blocks operating in synchronization with the plurality of internal clock signals generated by said internal clock signal generation means; and a plurality of signal transmission paths provided between said internal clock signal generation means and said plurality of internal circuit blocks, respectively, said plurality of signal transmission paths each transmitting an internal clock signal to a corresponding one of said internal circuit block from said internal clock signal generation means and transmitting the internal clock signal transmitted to said internal circuit block to said internal clock signal generation means as a feedback signal, said internal clock signal generation means including first select means receiving said external clock signal and first and second feedback signals among the plurality of feedback signals for selectively outputting a first pair of signals formed of said external clock signal and said first feedback signal and a second pair of signals formed of said first feedback signal and said second feedback signal, phase comparison means receiving the pair of signals of said first select means for comparing the phases of the pair of signals, voltage control oscillation means responsive to the output signal of said phase comparison means for generating a first internal clock signal, delay means delaying the first internal clock signal generated by said voltage control oscillation means for generating a second internal clock signal based on the output signal of said phase comparison means, second select means for selectively applying the output signal of said phase comparison means to said voltage control oscillation means and said delay means; and selective control means for controlling said first and second select means so that the output signal of said second select means is applied to said voltage control oscillation means when said first select means selects said first pair of signals and the output signal of said second select means is applied to said delay means when said first select means selects said second pair of signals.

Claim 5

A semiconductor integrated circuit device operating in synchronization with an internal clock signal generated based on an externally applied external clock signal, comprising: internal clock signal generation means responsive to the external clock signal for generating a plurality of internal clock signals of different phases, said internal clock signal generation means including phase locked loop means for synchronizing the phase of an internal clock signal to be fed back among said plurality of internal clock signals with the phase of the external clock signal; output latch means for latching a data signal to be output externally from said semiconductor integrated circuit device; signal selective supply means for selectively supplying the plurality of internal clock signals generated by said internal clock signal generation means to said output latch means, said output latch means latching the data signal in synchronization with the supplied internal clock signal; and an internal circuit block operating in synchronization with one of said plurality of internal clock signals for supplying said output latch means with said data signal to be externally output.

Claim 6

A semiconductor integrated circuit device operating in synchronization with an internal clock signal generated based on an externally applied external clock signal, comprising: internal clock signal generation means responsive to the external clock signal for generating a plurality of internal clock signals of different phases, said internal clock signal generation means including phase locked loop means for synchronizing the phase of an internal clock signal to be fed back among said plurality of internal clock signals with the phase of the external clock signal; output latch means for latching a data signal to be output externally from said semiconductor integrated circuit device; signal selective supply means for selectively supplying the plurality of internal clock signals generated by said internal clock signal generation means to said output latch means, said output latch means latching the data signal in synchronization with the supplied internal clock signal; and an internal circuit block operating in synchronization with one of said plurality of internal clock signals for supplying said output latch means with said data signal to be externally output.

Claim 7

A semiconductor integrated circuit device operating in synchronization with an internal clock signal generated based on an externally input external clock signal, comprising: internal clock signal generation means responsive to the external clock signal for generating a plurality of internal clock signals of different phases, said internal clock signal generation means including phase locked loop means for synchronizing the phase of an internal clock signal to be fed back among said plurality of internal clock signals with the phase of the external clock signal; input latch means for latching a data signal input externally to said semiconductor integrated circuit device; signal selective supply means for selectively supplying said input latch means with the plurality of internal clock signals generated by said internal clock signal generation means, said input latch means latching the data signal in synchronization with the supplied internal clock signal; and an internal circuit block operating in synchronization with one of said plurality of internal clock signals and performing a prescribed processing to the data signal latched by said input latch means.

Claim 8

A semiconductor integrated circuit device operating in synchronization with an internal clock signal generated based on an externally input external clock signal, comprising: internal clock signal generation means responsive to the external clock signal for generating a plurality of internal clock signals of different phases, said internal clock signal generation means including phase locked loop means for synchronizing the phase of an internal clock signal to be fed back among said plurality of internal clock signals with the phase of the external clock signal; input latch means for latching a data signal input externally to said semiconductor integrated circuit device; signal selective supply means for selectively supplying said input latch means with the plurality of internal clock signals generated by said internal clock signal generation means, said input latch means latching the data signal in synchronization with the supplied internal clock signal; and an internal circuit block operating in synchronization with one of said plurality of internal clock signals and performing a prescribed processing to the data signal latched by said input latch means.

Claim 9

A semiconductor integrated circuit device operating in synchronization with an internal clock signal generated based on an externally input external clock signal, comprising: internal clock signal generation means responsive to the input external clock signal for generating a plurality of internal clock signals of different phases, said internal clock signal generation means including phase locked loop means for synchronizing the phase of an internal clock signal to be fed back among said plurality of internal clock signals with the phase of the input external clock signal; a plurality of output latch means each for latching a data signal to be externally output from said semiconductor integrated circuit device; and a plurality of signal selective supply means provided corresponding to said plurality of output latch means, said plurality of signal selective supply means each for selectively supplying a corresponding output latch means with one of the plurality of internal clock signals generated by said internal clock signal generation means, said output latch means latching the data signal in synchronization with the supplied internal clock signal.

Claim 10

A semiconductor integrated circuit device operating in synchronization with an internal clock signal generated based on an externally input external clock signal, comprising: internal clock signal generation means responsive to the input external clock signal for generating a plurality of internal clock signals of different phases, said internal clock signal generation means including phase locked loop means for synchronizing the phase of an internal clock signal to be fed back among said plurality of internal clock signals with the phase of the input external clock signal; a plurality of output latch means each for latching a data signal to be externally output from said semiconductor integrated circuit device; and a plurality of signal selective supply means provided corresponding to said plurality of output latch means, said plurality of signal selective supply means each for selectively supplying a corresponding output latch means with one of the plurality of internal clock signals generated by said internal clock signal generation means, said output latch means latching the data signal in synchronization with the supplied internal clock signal.

Claim 11

The semiconductor integrated circuit device as recited in claim 5 , wherein said plurality of signal selective supply means supply said plurality of output latch means with the internal clock signals of different phases.

Claim 12

A semiconductor integrated circuit device operating in synchronization with an internal clock signal generated based on an externally input external clock signal, comprising: internal clock signal generation means responsive to the input external clock signal for generating a plurality of internal clock signals of different phases, said internal clock signal generation means including phase locked loop means for synchronizing the phase of an internal clock signal to be fed back among said plurality of internal clock signals with the phase of the input external clock signal; a plurality of input latch means each for latching a data signal input externally to said semiconductor integrated circuit device; and a plurality of signal selective supply means provided corresponding to said plurality of input latch means, said plurality of signal selective supply means each for selectively supplying a corresponding input latch means with one of the plurality of internal clock signals generated by said internal clock signal generation means, said input latch means latching the data signal in synchronization with the supplied internal clock signal.

Claim 13

A semiconductor integrated circuit device operating in synchronization with an internal clock signal generated based on an externally input external clock signal, comprising: internal clock signal generation means responsive to the input external clock signal for generating a plurality of internal clock signals of different phases, said internal clock signal generation means including phase locked loop means for synchronizing the phase of an internal clock signal to be fed back among said plurality of internal clock signals with the phase of the input external clock signal; a plurality of input latch means each for latching a data signal input externally to said semiconductor integrated circuit device; and a plurality of signal selective supply means provided corresponding to said plurality of input latch means, said plurality of signal selective supply means each for selectively supplying a corresponding input latch means with one of the plurality of internal clock signals generated by said internal clock signal generation means, said input latch means latching the data signal in synchronization with the supplied internal clock signal.

Claim 14

The semiconductor integrated circuit device as recited in claim 7 , wherein said plurality of signal selective supply means supplying said plurality of input latch means with the internal clock signals of different phases.