US6266750B1
Expired / Lapsed
US
⏱️ 0.0 years remaining
Variable length pipeline with parallel functional units
Assignee: Advanced Memory International Inc
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Filing: 1999-01-15
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Granted: 2001-07-24
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Expires: 2019-01-15
Abstract
Abstract Method and apparatus for implementing a variable length pipeline in a packet-driven memory control system, including a command front end and one or more parallel command sequencers. The command front end decodes an external command packet into an internal command and issues it to a selected one of the command sequencers. The command has associated therewith a desired latency value. A first group of one or more memory control steps for the given command is performed by the command front end if the desired latency value is less than a threshold latency value, or by the selected command sequencer if the desired latency value is greater than or equal to the threshold latency value. The remainder of the memory control steps required for the command are performed by the selected command sequencer. If the first control steps are to be performed by the selected command sequencer, then depending on the desired latency value, the command sequencer further may insert one or more wait states before doing so.
Inventors
- 👤 Paul W. DeMone
- 👤 Peter B. Gillingham
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 20:38
CPC Classifications
G; G06; G06F; G06F13/00; G06F13/38; G06F13/42; G06F13/4204; G06F13/4234; G06F13/4243
Claims Analysis
Total Claims: 33
Claim 1
Independent Claim
122 words
A memory system having a plurality of memories each having a command decoder front end receiving incoming command packets, and a set of at least one command sequencer, wherein said command decoder front end has facilities for (1) at least partially decoding incoming command packets, (2) issuing commands to at least one sequencer in said set of command sequencers in response to said incoming command packets, and (3) performing a first group of at least one memory control step of a decoded command in response to said incoming command packets, and wherein each of said command sequencers has facilities for performing a second group of memory control steps of decoded commands issued to the command sequencer from the command decoder front end.
Claim 2
Dependent Claim
122 words
A memory system having a plurality of memories each having a command decoder front end receiving incoming command packets, and a set of at least one command sequencer, wherein said command decoder front end has facilities for (1) at least partially decoding incoming command packets, (2) issuing commands to at least one sequencer in said set of command sequencers in response to said incoming command packets, and (3) performing a first group of at least one memory control step of a decoded command in response to said incoming command packets, and wherein each of said command sequencers has facilities for performing a second group of memory control steps of decoded commands issued to the command sequencer from the command decoder front end.
Claim 3
Dependent Claim
33 words
A system according to claim 1 , wherein said command decoder front end further has facilities for assembling each of said incoming command packets from a respective plurality of consecutive incoming command words.
Claim 4
Dependent Claim
36 words
A system according to claim 1 , wherein said command decoder front end further has facilities for determining whether or not to perform said first group of memory control steps for a given incoming command packet.
Claim 5
Dependent Claim
66 words
A system according to claim 1 , wherein each of said incoming command packets has associated therewith a respective desired latency value, and wherein said command decoder front end further has facilities for performing said first group of memory control steps for a given incoming command packet only if the desired latency value associated with said given command packet is below a predetermined threshold latency value.
Claim 6
Dependent Claim
52 words
A system according to claim 4 , wherein each of said command sequencers further has facilities for performing said first group of memory control steps for said given incoming command packet, if said command decoder front end does not perform said first group of memory control steps for said given incoming command.
Claim 7
Dependent Claim
49 words
A system according to claim 4 , wherein said incoming command packets include a command type indicator, and wherein said command decoder front end includes facilities to determine the desired latency value for the given command packet in dependence upon the command type indicator in the given command packet.
Claim 8
Dependent Claim
62 words
A system according to claim 1 , wherein the facilities of said command decoder front end for issuing commands to at least one sequencer in response to said incoming command packets, issues such commands for a given incoming command packet substantially simultaneously with the performance by said command decoder front end of a memory control step for said given incoming command packet.
Claim 9
Independent Claim
101 words
A method for managing a memory system, for use with an incoming command packet, comprising the steps of: receiving said incoming command packet in a command decoder front end; said command decoder front end decoding said command packet, issuing a command to a first command sequencer in response to said command packet, and further performing a first group of at least one memory control step in response to said incoming command packet; and said first command sequencer performing a second group of at least one memory control step in response to receipt of said command from said command decoder front end.
Claim 10
Independent Claim
101 words
A method for managing a memory system, for use with an incoming command packet, comprising the steps of: receiving said incoming command packet in a command decoder front end; said command decoder front end decoding said command packet, issuing a command to a first command sequencer in response to said command packet, and further performing a first group of at least one memory control step in response to said incoming command packet; and said first command sequencer performing a second group of at least one memory control step in response to receipt of said command from said command decoder front end.
Claim 11
Dependent Claim
24 words
A method according to claim 8 , further comprising the step of assembling said command packet from a plurality of consecutive incoming command words.
Claim 12
Dependent Claim
59 words
A method according to claim 8 , further comprising the step of said first command sequencer determining that said first group of memory control steps, are performed by said command decoder front end, further comprising the step of said first command sequencer abstaining from performing said first group of memory control steps in response to said step of determining.
Claim 13
Dependent Claim
61 words
A method according to claim 8 , wherein said step of said command decoder front end issuing a command to a first command sequencer in response to said incoming command packet occurs substantially simultaneously with the step of said command decoder front end performing a first group of at least one memory control step in response to said incoming command packet.
Claim 14
Dependent Claim
97 words
A method according to claim 8 , further comprising the steps of: said command decoder front end further indicating a latency value to said first command sequencer in conjunction with said step of said command decoder issuing a command to a first command sequencer; and said first command sequencer inserting at least one latency wait state in dependence upon said latency value indicated by said command decoder front end, after receipt of said command from said command decoder front end and prior to said step of performing a second group of at least one memory control step.
Claim 15
Dependent Claim
38 words
A method according to claim 8 , further comprising the step of said command decoder front end selecting said first command sequencer from among a plurality of parallel command sequencers in response to receipt of said command packet.
Claim 16
Independent Claim
107 words
A method for managing a memory system, for use with a first incoming command packet, comprising the steps of: receiving said first incoming command packet in a command decoder front end; said command decoder front end decoding said first command packet, issuing a command to a first command sequencer in response to said first command packet, and determining whether to perform a first group of at least one memory control step in response to said first command packet; and said first command sequencer performing a second group of at least one memory control step in response to receipt of said command from said command decoder front end.
Claim 17
Independent Claim
107 words
A method for managing a memory system, for use with a first incoming command packet, comprising the steps of: receiving said first incoming command packet in a command decoder front end; said command decoder front end decoding said first command packet, issuing a command to a first command sequencer in response to said first command packet, and determining whether to perform a first group of at least one memory control step in response to said first command packet; and said first command sequencer performing a second group of at least one memory control step in response to receipt of said command from said command decoder front end.
Claim 18
Dependent Claim
24 words
A method according to claim 14 , further comprising the step of assembling said command packet from a plurality of consecutive incoming command words.
Claim 19
Dependent Claim
64 words
A method according to claim 14 , wherein said command decoder front end determines to perform said first group of memory control steps, further comprising the step of said command decoder front end performing said first group of memory control steps in response to said first command packet, wherein said second group of memory control steps excludes said first group of memory control steps.
Claim 20
Dependent Claim
58 words
A method according to claim 16 , wherein said step of said command decoder front end issuing a command to a first command sequencer in response to said first command packet occurs substantially simultaneously with said step of said command decoder front end performing said first group of memory control steps in response to said first command packet.
Claim 21
Dependent Claim
68 words
A method according to claim 14 , wherein each of said incoming command packets has associated therewith a respective desired latency value, and wherein said command decoder front end performs said step of determining whether to perform said first group of memory control steps in response to a determination of whether the desired latency value associated with said first command packet is below a predetermined threshold latency value.
Claim 22
Dependent Claim
73 words
A method according to claim 18 , wherein said command decoder front end determines that the desired latency value associated with said first command packet is below said predetermined threshold latency value, further comprising the step of said command decoder front end performing said first group of memory control steps in response to said first command packet, wherein said second group of memory control steps excludes said first group of memory control steps.
Claim 23
Dependent Claim
63 words
A method according to claim 18 , wherein said command decoder front end determines that the desired latency value associated with said first command packet is not below said predetermined threshold latency value, further comprising the step of said first command sequencer performing said first group of memory control steps in response to receipt of said command from said command decoder front end.
Claim 24
Dependent Claim
50 words
A method according to claim 18 , wherein said incoming command packets include a command type indicator, further comprising the step of wherein said command decoder front end determining the desired latency value for said first command packet in dependence upon the command type indicator in the first command packet.
Claim 25
Dependent Claim
97 words
A method according to claim 14 , further comprising the steps of: said command decoder front end further indicating a latency value to said first command sequencer in conjunction with said step of said command decoder issuing a command to a first command sequencer; and said first command sequencer inserting at least one latency wait state in dependence upon said latency value indicated by said command decoder front end, after receipt of said command from said command decoder front end and prior to said step of performing a second group of at least one memory control step.
Claim 26
Dependent Claim
38 words
A method according to claim 14 , further comprising the step of said command decoder front end selecting said first command sequencer from among a plurality of parallel command sequencers in response to receipt of said command packet.
Claim 27
Independent Claim
157 words
A method of operating a memory device for use in a packet-driven memory system comprising the steps of: receiving external command packets in a command front end circuit; decoding said external command packets into internal commands in said command front end circuit; issuing said internal commands to respective selected ones of a plurality of command sequencers; receiving each of said internal commands from the command front end circuit into the respective selected sequencer; performing a first group of control steps for a respective given internal command decoded from each given one of said external command packets, either in the command front end circuit or in the sequencer selected for the given internal command, selectably in dependence upon a comparison of a latency value associated with the given external command packet with a threshold latency value; and performing a second group of control steps for the given internal command in the sequencer selected for the given internal command.
Claim 28
Independent Claim
157 words
A method of operating a memory device for use in a packet-driven memory system comprising the steps of: receiving external command packets in a command front end circuit; decoding said external command packets into internal commands in said command front end circuit; issuing said internal commands to respective selected ones of a plurality of command sequencers; receiving each of said internal commands from the command front end circuit into the respective selected sequencer; performing a first group of control steps for a respective given internal command decoded from each given one of said external command packets, either in the command front end circuit or in the sequencer selected for the given internal command, selectably in dependence upon a comparison of a latency value associated with the given external command packet with a threshold latency value; and performing a second group of control steps for the given internal command in the sequencer selected for the given internal command.
Claim 29
Dependent Claim
87 words
A method according to claim 24 , further comprising the steps of: receiving in the command sequencer selected for each given internal command a latency indication from the command front end circuit; and entering a wait state for a selected number of clock cycles in dependence upon the command delay indication for each given internal command, after receipt of the given internal command in said step of receiving internal commands, and prior to said step of performing a second group of at least one memory control step.
Claim 30
Independent Claim
130 words
A method for processing commands in a memory system having a command module and multiple memory modules coupled together via command and data links, the method comprising the steps of: issuing a command packet from the command module to a selected memory module, the command packet having a latency value associated therewith; receiving the command packet in the selected memory module via a command decoder front end; decoding the issued command packet into an internal command; internally issuing the decoded command to a selected one of a plurality of parallel functional units; performing a first group of control actions in the command decoder front end if the latency value is less than a predetermined latency threshold; and performing a remaining group of control actions in the selected parallel functional unit.
Claim 31
Independent Claim
130 words
A method for processing commands in a memory system having a command module and multiple memory modules coupled together via command and data links, the method comprising the steps of: issuing a command packet from the command module to a selected memory module, the command packet having a latency value associated therewith; receiving the command packet in the selected memory module via a command decoder front end; decoding the issued command packet into an internal command; internally issuing the decoded command to a selected one of a plurality of parallel functional units; performing a first group of control actions in the command decoder front end if the latency value is less than a predetermined latency threshold; and performing a remaining group of control actions in the selected parallel functional unit.
Claim 32
Independent Claim
139 words
A method of operating a memory device for use in a packet-driven memory system comprising the steps of: receiving external command packets in a command front end circuit; decoding one of the external command packets to produce an internal command in the command front end circuit; issuing the internal command to a selected one of a plurality of command sequencers; performing a first group of control steps in the command front end circuit; receiving the internal command from the command front end circuit into the selected sequencer; receiving a command delay output from the command front end circuit into the selected sequencer; entering a wait state for a selected number of clock cycles if a latency value associated with the internal command is greater than a predetermined latency threshold, and executing remaining control steps in the selected command sequencer.
Claim 33
Independent Claim
139 words
A method of operating a memory device for use in a packet-driven memory system comprising the steps of: receiving external command packets in a command front end circuit; decoding one of the external command packets to produce an internal command in the command front end circuit; issuing the internal command to a selected one of a plurality of command sequencers; performing a first group of control steps in the command front end circuit; receiving the internal command from the command front end circuit into the selected sequencer; receiving a command delay output from the command front end circuit into the selected sequencer; entering a wait state for a selected number of clock cycles if a latency value associated with the internal command is greater than a predetermined latency threshold, and executing remaining control steps in the selected command sequencer.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2004-07-23 | 2005-01-22 | 2005-07-24 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2008-07-23 | 2009-01-22 | 2009-07-24 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2012-07-23 | 2013-01-22 | 2013-07-24 | $7700.00 | Window Closed / Lapsed |