US6088774A
Expired / Lapsed
US
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Read/write timing for maximum utilization of bidirectional read/write bus
Assignee: Advanced Memory International Inc
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Filing: 1997-09-19
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Granted: 2000-07-11
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Expires: 2017-09-19
Abstract
Abstract A method and apparatus for optimizing the efficiency of a data bus for a memory device. Extra latency is added between the time a memory controller issues a write instruction and the time the data is transferred on the data bus. This additional latency is optimized to reduce the number of idle time slots on the data bus when switching between a read instruction and a write instruction. Programmable registers are provided for adjusting the amount of latency.
Inventors
- 👤 Peter Bruce Gillingham
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 21:48
CPC Classifications
G; G11; G11C; G11C7/00; G11C7/10; G11C7/1051; G11C7/1066; G06; G06F; G06F13/00; G06F13/38; G06F13/42; G06F13/4204; G06F13/4234; G06F13/4243; G11C7/1006; G11C7/1012; G11C7/1057; G11C7/1072; G11C7/22; G11C2207/00; G11C2207/22; G11C2207/2254
Claims Analysis
Total Claims: 20
Claim 1
Independent Claim
84 words
A method of transferring data on a data bus to and from a memory device, comprising the steps of: issuing a read instruction to the memory device; transferring read data from the memory device after a first time period; issuing a write instruction to the memory device; and delaying a transfer of write data to the memory device for a second time period, wherein the length of the second time period is within two time slots of the length of the first time period.
Claim 2
Independent Claim
84 words
A method of transferring data on a data bus to and from a memory device, comprising the steps of: issuing a read instruction to the memory device; transferring read data from the memory device after a first time period; issuing a write instruction to the memory device; and delaying a transfer of write data to the memory device for a second time period, wherein the length of the second time period is within two time slots of the length of the first time period.
Claim 3
Dependent Claim
44 words
The method of claim 1, wherein a relationship of length of the second time period to length of the first time period is selected to allow the read data and the write data to be transferred on the data bus in consecutive time slots.
Claim 4
Dependent Claim
15 words
The method of claim 1 wherein the read instruction is issued after the write instruction.
Claim 5
Dependent Claim
23 words
The method of claim 3, wherein the read instruction is issued during a time slot immediately following the issuance of the write instruction.
Claim 6
Dependent Claim
24 words
The method of claim 1, wherein the difference between the first time period and the second time period is less than one clock cycle.
Claim 7
Dependent Claim
23 words
The method of claim 1, wherein the first time period is three time slots and the second time period is three time slots.
Claim 8
Dependent Claim
20 words
The method of claim 1, further comprising programming the length of the second time period in a first programmable register.
Claim 9
Dependent Claim
20 words
The method of claim 7, further comprising programming the length of the first time period in a second programmable register.
Claim 10
Dependent Claim
116 words
A memory system, comprising: a memory device; a command bus for transferring read instructions and write instructions to the memory device; a data bus for transferring read data from the memory device in response to read instructions, the read data being transferred on the data bus a first time period after the read instruction, and for transferring write data to the memory device in response to write instructions, the write data being transferred on the data bus a second time period after the write instruction; and a memory controller for controlling the flow of data on the data bus, wherein the length of the second time period is subject to control of a first programmable register.
Claim 11
Dependent Claim
116 words
A memory system, comprising: a memory device; a command bus for transferring read instructions and write instructions to the memory device; a data bus for transferring read data from the memory device in response to read instructions, the read data being transferred on the data bus a first time period after the read instruction, and for transferring write data to the memory device in response to write instructions, the write data being transferred on the data bus a second time period after the write instruction; and a memory controller for controlling the flow of data on the data bus, wherein the length of the second time period is subject to control of a first programmable register.
Claim 12
Dependent Claim
16 words
The memory system of claim 9, wherein the read instruction is issued after the write instruction.
Claim 13
Dependent Claim
44 words
The memory system of claim 9, wherein a relationship of the length of the second time period to the length of the first time period allows the read data and the write data to be transferred in consecutive time slots on a data bus.
Claim 14
Dependent Claim
25 words
The memory system of claim 9, wherein the difference between the first time period and the second time period is less than one clock cycle.
Claim 15
Dependent Claim
24 words
The memory system of claim 9, wherein the first time period is three time slots and the second time period is three time slots.
Claim 16
Dependent Claim
27 words
The memory system of claim 9, wherein the length of the second time period is within two time slots of the length of the first time period.
Claim 17
Dependent Claim
24 words
The memory system of claim 9, further comprising a second programmable register, wherein the first time period is programmed in the second programmable register.
Claim 18
Dependent Claim
123 words
A memory device, comprising: a data bus; first and second memory array banks coupled to said data bus; first and second delay registers, the first delay register specifying a first time period and the second delay register specifying a second time period; and a command decoder for receiving a write instruction for the first memory array bank and a read instruction for the second memory array bank, wherein data is transferred on the data bus to the first memory array bank following a delay of the first time period after the command decoder receives the write instruction, and data is transferred to the second memory array bank following a delay of the second time period after the command decoder receives the write instruction.
Claim 19
Dependent Claim
123 words
A memory device, comprising: a data bus; first and second memory array banks coupled to said data bus; first and second delay registers, the first delay register specifying a first time period and the second delay register specifying a second time period; and a command decoder for receiving a write instruction for the first memory array bank and a read instruction for the second memory array bank, wherein data is transferred on the data bus to the first memory array bank following a delay of the first time period after the command decoder receives the write instruction, and data is transferred to the second memory array bank following a delay of the second time period after the command decoder receives the write instruction.
Claim 20
Dependent Claim
25 words
The memory device of claim 16, wherein the difference between the first time period and the second time period is less than one clock cycle.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2003-07-11 | 2004-01-10 | 2004-07-11 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2007-07-11 | 2008-01-10 | 2008-07-11 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2011-07-11 | 2012-01-10 | 2012-07-11 | $7700.00 | Window Closed / Lapsed |