US5784582A
Expired / Lapsed
US
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Data processing system having memory controller for supplying current request and next request for access to the shared memory pipeline
Assignee: HP Inc
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Filing: 1996-10-28
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Granted: 1998-07-21
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Expires: 2016-10-28
Abstract
Abstract A router includes synchronous dynamic random access memory (SDRAM) based shared memory, with a controller configured to control the order in which the SDRAM access is granted to a plurality of interfaced components. In one embodiment, the controller's configuration minimizes the amount of time data from a particular source must wait to be read to and written from the SDRAM, and thus minimizes latency. In a different embodiment, the controller's configuration maximizes the amount of data read to and written from said SDRAM in a given amount of time and thus maximizes bandwidth. In yet another embodiment, characteristics of the latency minimization embodiment and the bandwidth maximization embodiment are combined to create a hybrid configuration.
Inventors
- 👤 John H. Hughes
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 00:32
CPC Classifications
G; G11; G11C; G11C7/00; G11C7/10; G11C7/1072; G06; G06F; G06F13/00; G06F13/14; G06F13/16; G06F13/1605; G06F13/161; G06F13/1615
Claims Analysis
Total Claims: 19
Claim 1
Independent Claim
116 words
A data processing system, comprising; a shared memory comprising synchronous dynamic random access memory SDRAM and a shared memory pipeline coupled to the SDRAM, which executes read, write and refresh requests for access in a pipeline fashion; a plurality of data paths coupled to the shared memory which generate requests for access to the shared memory, the requests having characteristics including a starting address, a length and a type; and a memory controller, coupled to the plurality of data paths, which stores requests from the plurality of data paths, supplies a current request for access to the shared memory pipeline, and selects from the stored requests, a next request for access for the shared memory pipeline.
Claim 2
Dependent Claim
116 words
A data processing system, comprising; a shared memory comprising synchronous dynamic random access memory SDRAM and a shared memory pipeline coupled to the SDRAM, which executes read, write and refresh requests for access in a pipeline fashion; a plurality of data paths coupled to the shared memory which generate requests for access to the shared memory, the requests having characteristics including a starting address, a length and a type; and a memory controller, coupled to the plurality of data paths, which stores requests from the plurality of data paths, supplies a current request for access to the shared memory pipeline, and selects from the stored requests, a next request for access for the shared memory pipeline.
Claim 3
Dependent Claim
47 words
The data processing system of claim 1, wherein the memory controller includes logic responsive to the characteristics of the request or requests currently in the shared memory pipeline, and to the characteristics of the pending requests to select a next request for access to improve pipeline fullness.
Claim 4
Dependent Claim
25 words
The data processing system of claim 1, wherein the memory controller includes logic responsive to a configuration parameter to select a next request for access.
Claim 5
Dependent Claim
28 words
The data processing system of claim 3, wherein the configuration parameter comprises a data path priority to manage latency of stored requests from the plurality of data paths.
Claim 6
Dependent Claim
54 words
The data processing system of claim 1, wherein the memory controller includes logic responsive to the characteristics of a request currently in the shared memory pipeline, and to the characteristics of the pending requests to give priority to a next request for access of the same type as the request currently in the pipeline.
Claim 7
Dependent Claim
82 words
The data processing system of claim 1, wherein the SDRAM includes a column buffer which stores lines of data being accessed in response to a request currently in the pipeline, and the memory controller includes logic responsive to the characteristics of the request currently in the shared memory pipeline, and to the characteristics of the pending requests to give priority to a next request for access to the line of data in the column buffer for the request currently in the pipeline.
Claim 8
Dependent Claim
64 words
The data processing system of claim 1, wherein the SDRAM includes a first bank and a second bank accessible independently, and the memory controller includes logic responsive to the characteristics of a request currently in the shared memory pipeline to the first bank, and to the characteristics of the pending requests to give priority to a next request for access to the second bank.
Claim 9
Dependent Claim
144 words
A network intermediate system, comprising: a backplane bus coupled to a plurality of input/output nodes; a central processing node coupled to the backplane bus, including a host processor and a shared memory comprising synchronous dynamic random access memory SDRAM and a shared memory pipeline coupled to the SDRAM, which executes read, write and refresh requests for access in a pipeline fashion; the host processor and the plurality of input/output nodes generating requests for access to the shared memory, the requests having characteristics including a starting address, a length and a type; and a memory controller, coupled to the host processor and the backplane bus, which stores requests from the host processor and the plurality of input/output nodes, supplies a current request for access to the shared memory pipeline, and selects from the stored requests, a next request for access for the shared memory pipeline.
Claim 10
Dependent Claim
144 words
A network intermediate system, comprising: a backplane bus coupled to a plurality of input/output nodes; a central processing node coupled to the backplane bus, including a host processor and a shared memory comprising synchronous dynamic random access memory SDRAM and a shared memory pipeline coupled to the SDRAM, which executes read, write and refresh requests for access in a pipeline fashion; the host processor and the plurality of input/output nodes generating requests for access to the shared memory, the requests having characteristics including a starting address, a length and a type; and a memory controller, coupled to the host processor and the backplane bus, which stores requests from the host processor and the plurality of input/output nodes, supplies a current request for access to the shared memory pipeline, and selects from the stored requests, a next request for access for the shared memory pipeline.
Claim 11
Dependent Claim
47 words
The network intermediate system of claim 8, wherein the memory controller includes logic responsive to the characteristics of the request or requests currently in the shared memory pipeline, and to the characteristics of the pending requests to select a next request for access to improve pipeline fullness.
Claim 12
Dependent Claim
25 words
The network intermediate system of claim 8, wherein the memory controller includes logic responsive to a configuration parameter to select a next request for access.
Claim 13
Dependent Claim
30 words
The network intermediate system of claim 10, wherein the configuration parameter comprises priority values to manage latency of stored requests, from the host processor and the plurality of input/output nodes.
Claim 14
Dependent Claim
51 words
The network intermediate system of claim 8, wherein the memory controller includes logic responsive to the characteristics of a request currently in the shared memory pipeline, and to the characteristics of the pending requests to a next request for access of the same type as the request currently in the pipeline.
Claim 15
Dependent Claim
82 words
The network intermediate system of claim 8, wherein the SDRAM includes a column buffer which stores lines of data being accessed in response to a request currently in the pipeline, and the memory controller includes logic responsive to the characteristics of the request currently in the shared memory pipeline, and to the characteristics of the pending requests to give priority to a next request for access to the line of data in the column buffer for the request currently in the pipeline.
Claim 16
Dependent Claim
61 words
The network intermediate system of claim 8, wherein the SDRAM includes a first bank and a second bank accessible independently, and the memory controller includes logic responsive to the characteristics of a request currently in the shared memory pipeline to the first bank, and to the characteristics of the pending requests to a next request for access to the second bank.
Claim 17
Dependent Claim
38 words
The network intermediate system of claim 8, wherein the central processing node includes a host input/output node which generates requests for access to the shared memory, and the memory controller also stores requests from the host input/output node.
Claim 18
Dependent Claim
178 words
A network intermediate system, comprising: a backplane bus coupled to a plurality of input/output nodes; a central processing node coupled to the backplane bus, including a host processor and a shared memory comprising synchronous dynamic random access memory SDRAM and a shared memory pipeline coupled to the SDRAM, which executes read, write and refresh requests for access in a pipeline fashion; the host processor and the plurality of input/output nodes generating requests for access to the shared memory, the requests having characteristics including a starting address, a length and a type; and a memory controller, coupled to the host processor and the backplane bus, which stores requests from the host processor and the plurality of input/output nodes, supplies a current request for access to the shared memory pipeline, and selects from the stored requests, a next request for access for the shared memory pipeline, including logic responsive to the characteristics of a request currently in the shared memory pipeline, and to the characteristics of the pending requests to select a next request for access to improve pipeline fullness.
Claim 19
Dependent Claim
178 words
A network intermediate system, comprising: a backplane bus coupled to a plurality of input/output nodes; a central processing node coupled to the backplane bus, including a host processor and a shared memory comprising synchronous dynamic random access memory SDRAM and a shared memory pipeline coupled to the SDRAM, which executes read, write and refresh requests for access in a pipeline fashion; the host processor and the plurality of input/output nodes generating requests for access to the shared memory, the requests having characteristics including a starting address, a length and a type; and a memory controller, coupled to the host processor and the backplane bus, which stores requests from the host processor and the plurality of input/output nodes, supplies a current request for access to the shared memory pipeline, and selects from the stored requests, a next request for access for the shared memory pipeline, including logic responsive to the characteristics of a request currently in the shared memory pipeline, and to the characteristics of the pending requests to select a next request for access to improve pipeline fullness.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2001-07-20 | 2002-01-19 | 2002-07-21 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-07-20 | 2006-01-19 | 2006-07-21 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2009-07-20 | 2010-01-19 | 2010-07-21 | $7700.00 | Window Closed / Lapsed |