Patent US6261887B1 successfully refreshed from Google Patents.
US6261887B1
Expired / Lapsed
US
⏱️ 0.0 years remaining
Transistors with independently formed gate structures and method
Assignee: Texas Instruments Inc
•
Filing: 1998-08-19
•
Granted: 2001-07-17
•
Expires: 2018-08-19
Abstract
Abstract Transistors may be fabricated by isolating a first region ( 16 ) of a semiconductor layer from a second region ( 18 ) of the semiconductor layer ( 12 ). A first disposable gate structure ( 26 ) of the first transistor may be formed over the first region ( 16 ) of the semiconductor layer ( 12 ). A second disposable gate structure ( 28 ) of the second, complementary transistor may be formed over the second region ( 18 ) of the semiconductor layer ( 12 ). A capping layer ( 60 ) may be formed over the first and second regions ( 16, 18 ) including the first and second disposable gate structures ( 26, 28 ). A portion ( 62, 64 ) of the first and second disposable gate structures ( 26, 28 ) may be exposed through the capping layer ( 60 ). A second disposable gate cap ( 66 ) may be formed over the exposed portion ( 64 ) of the second disposable gate structure ( 28 ) and at least part of the first disposable gate structure ( 26 ) removed. A first gate structure ( 70 ) of the first transistor may be formed in the place of removed part of the first disposable gate structure. In one embodiment, a second gate structure ( 80 ) of the second transistor may comprise the second disposable gate structure ( 28 ). In another embodiment, a first disposable gate cap ( 76 ) may be formed over the exposed portion ( 78 ) of the first gate structure and the second disposable gate cap ( 66 ) over the second disposable gate structure ( 28 ) may be removed. The second gate structure ( 80 ) of the second transistor may then be formed in the place of the removed second disposable gate structure ( 28 ).
Inventors
- 👤 Mark S. Rodder
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 06:33
CPC Classifications
H; H10; H10D; H10D62/00; H10D62/10; H10D62/13; H10D62/149; H10D62/151; H10D64/00; H10D64/01; H10D64/017; H10D64/20; H10D64/27; H10D64/311; H10D64/411; H10D64/511; H10D64/517; H10D64/518; H10D64/60; H10D64/66; H10D64/661; H10D64/662; H10D64/663; H10D64/665; H10D84/00; H10D84/01; H10D84/0123; H10D84/0126; H10D84/0165; H10D84/0172; H10D84/0177; H10D84/02; H10D84/03; H10D84/038; Y; Y10; Y10S; Y10S438/00; Y10S438/902
Claims Analysis
Total Claims: 22
Claim 1
Independent Claim
160 words
A method of fabricating a semiconductor device, comprising the steps of: isolating a first region of a semiconductor layer from a second region of the semiconductor layer; forming a first disposable gate structure of a first transistor over the first region of the semiconductor layer; forming a second disposable gate structure of a second transistor over the second region of the semiconductor layer; forming a capping layer over the first and second regions except over a portion of the first and second disposable gate structures; forming a second disposable gate cap over the exposed portion of the second disposable gate structure; removing at least part of the first disposable gate structure; and after removing at least a part of the first disposable gate structure and prior to removing the second disposable gate cap, depositing a first gate body material of a first gate structure of the first transistor in place of the removed part of the first disposable gate structure.
Claim 2
Independent Claim
160 words
A method of fabricating a semiconductor device, comprising the steps of: isolating a first region of a semiconductor layer from a second region of the semiconductor layer; forming a first disposable gate structure of a first transistor over the first region of the semiconductor layer; forming a second disposable gate structure of a second transistor over the second region of the semiconductor layer; forming a capping layer over the first and second regions except over a portion of the first and second disposable gate structures; forming a second disposable gate cap over the exposed portion of the second disposable gate structure; removing at least part of the first disposable gate structure; and after removing at least a part of the first disposable gate structure and prior to removing the second disposable gate cap, depositing a first gate body material of a first gate structure of the first transistor in place of the removed part of the first disposable gate structure.
Claim 3
Dependent Claim
81 words
The method of claim 1 , further comprising the steps of: forming a first disposable gate cap over an exposed portion of the first gate structure; removing the second disposable gate cap over the second disposable gate structure; removing at least part of the second disposable gate structure; and after depositing the first gate body, depositing a second gate body of the second gate structure of the second transistor in place of the removed part of the second disposable gate structure.
Claim 4
Dependent Claim
22 words
The method of claim 2 , further comprising the step of removing the first disposable gate cap over the first gate structure.
Claim 5
Dependent Claim
29 words
The method of claim 2 , further comprising the step of in-situ doping the first gate body and further comprising the step of in-situ doping the second gate body.
Claim 6
Dependent Claim
25 words
The method of claim 2 , wherein the first gate body comprises a first material and the second gate body comprises a second, disparate material.
Claim 7
Dependent Claim
12 words
The method of claim 5 , wherein the first material comprises platinum.
Claim 8
Dependent Claim
12 words
The method of claim 5 , wherein the second material comprises aluminum.
Claim 9
Dependent Claim
34 words
The method of claim 5 , wherein the first transistor comprises a p-type transistor, the second transistor comprises a n-type transistor and the gate body of at least one of the transistors is metallic.
Claim 10
Dependent Claim
34 words
The method of claim 5 , wherein the first transistor comprises a n-type transistor, the second transistor comprises a p-type transistor and the gate body of at least one of the transistors is metallic.
Claim 11
Dependent Claim
15 words
The method of claim 1 , wherein the first and second transistors comprise CMOS transistors.
Claim 12
Dependent Claim
17 words
The method of claim 1 , wherein the first and second transistors comprise CMOS field effect transistors.
Claim 13
Dependent Claim
27 words
The method of claim 1 , wherein the first and second disposable gate structures comprise n-type gate material and the first gate structure comprises p-type gate material.
Claim 14
Dependent Claim
27 words
The method of claim 1 , wherein the first and second disposable gate structures comprise p-type gate material and the first gate structure comprises n-type gate material.
Claim 15
Dependent Claim
64 words
The method of claim 1 , the steps of forming the first and second disposable gate structures each further comprising the steps of: forming a buffer segment over semiconductor layer to prevent etching of the semiconductor layer during removal of a readily etchable segment of the disposable gate structure; and forming the readily etchable segment of the disposable gate structure over the buffer segment.
Claim 16
Dependent Claim
15 words
The method of claim 14 , wherein the readily etchable segment comprises a non-nitride material.
Claim 17
Dependent Claim
65 words
The method of claim 14 , the step of forming the capping layer over the first and second regions further comprising the steps of; depositing the capping layer at least to a level of the readily etchable segments of the first and second disposable gate structures; and planarizing the capping layer to expose the readily etchable segments of the first and second disposable gate structures.
Claim 18
Dependent Claim
18 words
The method of claim 2 , wherein a dielectric of the first disposable gate structure is not removed.
Claim 19
Dependent Claim
20 words
The method of claim 2 , wherein a dielectric of the first and second disposable gate structures are not removed.
Claim 20
Dependent Claim
105 words
The method of claim 1 , further comprising the steps of: forming an insulating layer over the first and second regions including the first and second disposable gate structures; removing a portion of the insulating layer over the first region to leave a first sidewall insulator about the first disposable gate structure; forming a source and a drain of the first transistor; masking the first region including the source and drain; removing a portion of the insulating layer over the second region to leave a second sidewall insulator about the second disposable gate structure; and forming a source and a drain of the second transistor.
Claim 21
Independent Claim
189 words
A method of fabricating an integrated circuit chip, comprising the steps of: isolating a first region of a semiconductor layer from a second region of the semiconductor layer; forming a first disposable gate structure of a first transistor over the first region of the semiconductor layer; forming a second disposable gate structure of a second transistor over the second region of the semiconductor layer; forming a capping layer over the first and second regions except over a portion of the first and second disposable gate structures; forming a second disposable gate cap over the exposed portion of the second disposable gate structure; removing the first disposable gate structure; forming a first gate dielectric over the first region where the first disposable gate structure was removed; depositing a first gate body over the first gate dielectric; forming a first disposable gate cap over the first gate body; then, removing the second disposable gate cap and the second disposable gate structure; then, forming a second gate dielectric over the second region where the second disposable gate structure was removed; and then depositing a second gate body over the second gate dielectric.
Claim 22
Independent Claim
189 words
A method of fabricating an integrated circuit chip, comprising the steps of: isolating a first region of a semiconductor layer from a second region of the semiconductor layer; forming a first disposable gate structure of a first transistor over the first region of the semiconductor layer; forming a second disposable gate structure of a second transistor over the second region of the semiconductor layer; forming a capping layer over the first and second regions except over a portion of the first and second disposable gate structures; forming a second disposable gate cap over the exposed portion of the second disposable gate structure; removing the first disposable gate structure; forming a first gate dielectric over the first region where the first disposable gate structure was removed; depositing a first gate body over the first gate dielectric; forming a first disposable gate cap over the first gate body; then, removing the second disposable gate cap and the second disposable gate structure; then, forming a second gate dielectric over the second region where the second disposable gate structure was removed; and then depositing a second gate body over the second gate dielectric.
References Cited (Backward Citations)
JPS6045053A
Cited
US4948745A
Cited
US5021354A
Cited
US5168072A
Cited
US5397909A
Cited
US5716861A
Cited
US5384729A
Cited
US5654242A
Cited
EP0727815A2
Cited
US5956591A
Cited
US5976924A
Cited
US5994193A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2004-07-16 | 2005-01-15 | 2005-07-17 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2008-07-16 | 2009-01-15 | 2009-07-17 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2012-07-16 | 2013-01-15 | 2013-07-17 | $7700.00 | Window Closed / Lapsed |