US6260094B1
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method and apparatus providing programmable decode modes for secondary PCI bus interfaces
Assignee: Intel Corp
•
Filing: 1998-08-13
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Granted: 2001-07-10
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Expires: 2018-08-13
Abstract
Abstract A PCI-to-PCI having programmable decode modes comprising at least one of a standard bridge data transfer transaction, an intelligent bridge data transfer transaction, and a private address space data transfer transaction, and wherein the transactions are configured to bypass a host bus.
Inventors
- 👤 Barry R. Davis
- 👤 Scott Goble
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 18:15
CPC Classifications
G; G06; G06F; G06F13/00; G06F13/38; G06F13/40; G06F13/4004; G06F13/4027; G06F13/404
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
44 words
A PCI-to-PCI bridge, having programmable decode modes, said programmable decode modes comprising at least one of standard bridge data transfer transactions, intelligent bridge data transfer transactions, and private address space data transfer transactions, and wherein the transactions are configured to bypass a host bus.
Claim 2
Dependent Claim
44 words
A PCI-to-PCI bridge, having programmable decode modes, said programmable decode modes comprising at least one of standard bridge data transfer transactions, intelligent bridge data transfer transactions, and private address space data transfer transactions, and wherein the transactions are configured to bypass a host bus.
Claim 3
Dependent Claim
44 words
The bridge of claim 1 wherein the programmable decode mode for intelligent bridge data transfer transactions disables inverse positive decode operations within a primary address space of a secondary PCI bus; and enables reverse positive decoding within selected portions of the primary address base.
Claim 4
Dependent Claim
30 words
The bridge of claim 1 wherein the programmable decode mode for subtractive operations: captures any transactions on the secondary PCI bus not claimed after a predetermined number of clock cycles.
Claim 5
Independent Claim
48 words
A device comprising: a PCI-to-PCI bridge having programmable decode modes wherein the PCI-to-PCI bridge is coupled to a primary PCI bus and a secondary PCI bus; the secondary PCI bus having a secondary PCI interface which captures unclaimed subtractive routing data transfer operations on the secondary PCI bus.
Claim 6
Dependent Claim
47 words
A PCI-to-PCI bridge, having programmable decode modes, said programmable decode modes comprising at least one of a standard bridge data transfer transaction, an intelligent bridge data transfer transaction, and a private address space data transfer transaction, and wherein the transactions are configured to bypass a host bus.
Claim 7
Dependent Claim
47 words
A PCI-to-PCI bridge, having programmable decode modes, said programmable decode modes comprising at least one of a standard bridge data transfer transaction, an intelligent bridge data transfer transaction, and a private address space data transfer transaction, and wherein the transactions are configured to bypass a host bus.
References Cited (Backward Citations)
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2004-07-09 | 2005-01-08 | 2005-07-10 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2008-07-09 | 2009-01-08 | 2009-07-10 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2012-07-09 | 2013-01-08 | 2013-07-10 | $7700.00 | Window Closed / Lapsed |