US6259130B1
Expired / Lapsed
US
⏱️ 0.0 years remaining
High density flash memories with high capacitive-couping ratio and high speed operation
Assignee: Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Filing: 1999-03-09
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Granted: 2001-07-10
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Expires: 2019-03-09
Abstract
Abstract The device includes a gate oxide formed on a semiconductor substrate. Oxide regions are respectively formed on the substrate and adjacent to the gate oxide. Textured oxides are formed on the substrate, between the gate oxide and the oxide regions. A floating gate consists of a first polysilicon portion, second polysilicon portions and a third portion that is composed of hemisperical grained silicon (HSG-Si). The first polysilicon portion is formed on the gate oxide. Isolations are formed on the side walls of the first polysilicon portion. The second polysilicon portions are respectively formed next to the isolations and over a portion of the oxide regions. The HSG-Si is formed on the upper surface of the first polysilicon portion and the second polysilicon portions. A dielectric layer is formed on the HSG-Si of the floating gate. A control gate is formed on the dielectric layer. The doped regions are formed in the substrate and under the textured oxides and the oxide regions.
Inventors
- 👤 Shye-Lin Wu
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-03 19:02
CPC Classifications
H; H10; H10D; H10D64/00; H10D64/01; H10D64/013; H10D64/01302; H10D64/01332; H10D64/01336; H10D64/0134; H10D30/00; H10D30/01; H10D30/021; H10D30/0411; H10D64/01344; H10D64/031; H10D64/035; H10D64/60; H10D64/66; H10D64/68; H10D64/693; H10D64/01342; H10D64/01346
Claims Analysis
Total Claims: 19
Claim 1
Independent Claim
172 words
A nonvolatile memory on a substrate, said nonvolatile memory comprising: a gate dielectric formed on said substrate; oxide regions respectively formed on said substrate and adjacent to said gate dielectric; textured oxides formed on said substrate, between said gate dielectric and said oxide regions; floating gate consisting of a first portion, second portions and a third portion, wherein said first portion of said floating gate formed on said gate dielectric, isolations being formed on the side walls of said first portion, said second portions being respectively formed next to said isolations and over a portion of said oxide regions, wherein said third portion of said floating gate having a rugged surface to increase the surface area is formed on the upper surface of said first portion and said second portions; a dielectric layer formed on said third portion of said floating gate, side walls of said second portions; a control gate formed on said dielectric layer; and doped regions formed in said substrate and under said textured oxides and said oxide regions.
Claim 2
Dependent Claim
172 words
A nonvolatile memory on a substrate, said nonvolatile memory comprising: a gate dielectric formed on said substrate; oxide regions respectively formed on said substrate and adjacent to said gate dielectric; textured oxides formed on said substrate, between said gate dielectric and said oxide regions; floating gate consisting of a first portion, second portions and a third portion, wherein said first portion of said floating gate formed on said gate dielectric, isolations being formed on the side walls of said first portion, said second portions being respectively formed next to said isolations and over a portion of said oxide regions, wherein said third portion of said floating gate having a rugged surface to increase the surface area is formed on the upper surface of said first portion and said second portions; a dielectric layer formed on said third portion of said floating gate, side walls of said second portions; a control gate formed on said dielectric layer; and doped regions formed in said substrate and under said textured oxides and said oxide regions.
Claim 3
Dependent Claim
14 words
The nonvolatile memory of claim 1 , wherein said gate oxide comprises silicon oxide.
Claim 4
Dependent Claim
14 words
The nonvolatile memory of claim 1 , wherein said textured oxides comprise silicon oxide.
Claim 5
Dependent Claim
17 words
The nonvolatile memory of claim 1 , wherein said first portion of said floating gate comprises polysilicon.
Claim 6
Dependent Claim
17 words
The nonvolatile memory of claim 1 , wherein said second portions of said floating gate comprise polysilicon.
Claim 7
Dependent Claim
15 words
The nonvolatile memory of claim 1 , wherein said third portion comprises semispherical grained silicon.
Claim 8
Dependent Claim
13 words
The nonvolatile memory of claim 1 , wherein said control gate comprises polysilicon.
Claim 9
Dependent Claim
13 words
The nonvolatile memory of claim 1 , wherein said dielectric layer comprises ONO.
Claim 10
Dependent Claim
13 words
The nonvolatile memory of claim 1 , wherein said dielectric layer comprises NO.
Claim 11
Dependent Claim
17 words
The nonvolatile memory of claim 1 , wherein said dielectric layer comprises Ta 2 O 5 .
Claim 12
Dependent Claim
177 words
A nonvolatile memory on a substrate, said nonvolatile memory comprising: a gate dielectric formed on said substrate; oxide regions respectively formed on said substrate and adjacent to said gate dielectric; textured oxides formed on said substrate, between said gate dielectric and said oxide regions; floating gate consisting of a first polysilicon portion, second polysilicon portions and a third portion composed of semispherical grained silicon, wherein said first polysilicon portion formed on said gate dielectric, isolations being formed on the side walls of said first polysilicon portion, said second polysilicon portions being respectively formed next to said isolations and over a portion of said oxide regions, wherein said semispherical grained silicon having a rugged surface to increase the surface area is formed on the upper surface of said first polysilicon portion and said second polysilicon portions; a dielectric layer formed on said third portion of said floating gate, side walls of said second portions; a control gate formed on said dielectric layer; and doped regions formed in said substrate and under said textured oxides and said oxide regions.
Claim 13
Dependent Claim
177 words
A nonvolatile memory on a substrate, said nonvolatile memory comprising: a gate dielectric formed on said substrate; oxide regions respectively formed on said substrate and adjacent to said gate dielectric; textured oxides formed on said substrate, between said gate dielectric and said oxide regions; floating gate consisting of a first polysilicon portion, second polysilicon portions and a third portion composed of semispherical grained silicon, wherein said first polysilicon portion formed on said gate dielectric, isolations being formed on the side walls of said first polysilicon portion, said second polysilicon portions being respectively formed next to said isolations and over a portion of said oxide regions, wherein said semispherical grained silicon having a rugged surface to increase the surface area is formed on the upper surface of said first polysilicon portion and said second polysilicon portions; a dielectric layer formed on said third portion of said floating gate, side walls of said second portions; a control gate formed on said dielectric layer; and doped regions formed in said substrate and under said textured oxides and said oxide regions.
Claim 14
Dependent Claim
14 words
The nonvolatile memory of claim 11 , wherein said gate oxide comprises silicon oxide.
Claim 15
Dependent Claim
14 words
The nonvolatile memory of claim 11 , wherein said textured oxides comprise silicon oxide.
Claim 16
Dependent Claim
13 words
The nonvolatile memory of claim 11 , wherein said control gate comprises polysilicon.
Claim 17
Dependent Claim
13 words
The nonvolatile memory of claim 11 , wherein said dielectric layer comprises ONO.
Claim 18
Dependent Claim
13 words
The nonvolatile memory of claim 11 , wherein said dielectric layer comprises NO.
Claim 19
Dependent Claim
17 words
The nonvolatile memory of claim 11 , wherein said dielectric layer comprises Ta 2 O 5 .
References Cited (Backward Citations)
US4099196A
Cited
US5087583A
Cited
US5208176A
Cited
US5089867A
Cited
US5972771A
Cited
US5635415A
Cited
US6043124A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2004-07-09 | 2005-01-08 | 2005-07-10 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2008-07-09 | 2009-01-08 | 2009-07-10 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2012-07-09 | 2013-01-08 | 2013-07-10 | $7700.00 | Window Closed / Lapsed |