Patent US6258649B1 successfully refreshed from Google Patents.
US6258649B1
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Semiconductor integrated circuit device and method of manufacturing the same
Assignee: Longitude Licensing Ltd
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Filing: 1999-09-03
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Granted: 2001-07-10
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Expires: 2019-09-03
Abstract
Abstract In order to improve connection reliability of a feeding interconnection connected to an electrode of each of the information storage capacitive elements of a DRAM, the formation of a through hole for connecting the information storage capacitive element formed over each memory cell selection MISFET and a feeding interconnection is performed in a process different from that for the formation of a through hole for connecting an interconnection of a second wiring layer in a peripheral circuit, which is formed over the information storage capacitive element and an interconnection corresponding to a first wiring layer.
Inventors
- 👤 Yoshitaka Nakamura
- 👤 Masayoshi Hirasawa
- 👤 Isamu Asano
- 👤 Tsuyoshi Tamaru
- 👤 Satoru Yamada
- 👤 Keizo Kawakita
- 👤 Toshihiro Sekiguchi
- 👤 Yoshitaka Tadaki
- 👤 Takuya Fukuda
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 03:12
CPC Classifications
H; H10; H10B; H10B12/00; H10B12/01; H10B12/09; H10D; H10D64/00; H10D64/01; H10D64/011; H10D64/0111; H10D64/0112; H10D64/01125; H10B12/30; H10B12/48; H10D1/00; H10D1/60; H10D1/68; H10P; H10P14/00; H10P14/60; H10P14/63; H10P14/6326; H10P14/6328; H10P14/6334; H10P14/6336; H10P14/66; H10P14/668; H10P14/6681; H10P14/6682; H10P14/69; H10P14/692; H10P14/6921; H10P14/69215; H10W; H10W20/00; H10W20/01; H10W20/031; H10W20/032; H10W20/033; H10W20/047; H10W20/071; H10W20/081; H10W20/089; H10W20/093; H10W20/097; H10W20/40; H10W20/41; H10W20/425
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
315 words
A method of manufacturing a semiconductor integrated circuit device, comprising the steps of: forming memory cell selection MISFETs in a memory array region on a main surface of a semiconductor substrate and forming MISFETs for a peripheral circuit in a peripheral circuit region; forming a first interconnection over the main surface of said semiconductor substrate with the MISFETs formed therein; forming a first insulating film over said first interconnection; defining grooves in said first insulating film in said memory array region; forming a first conductive film over said first insulating film including the interior of said grooves and forming a lower electrode of an information storage capacitive element inside said each groove; forming a second conductive film over said lower electrode with a capacitive insulating film interposed therebetween, and pattering said second conductive film to thereby form each upper electrode of said information storage capacitive element; forming a second insulating film over said each information storage capacitive element; defining a first through hole in an insulating film including said second insulating film and said first insulating film placed in a layer therebelow; forming a third conductive film over said second insulating film and patterning said third conductive film to thereby form a second interconnection electrically connected to said first interconnection via said first through hole; forming a third insulating film over said second interconnection; defining a second through hole in said third insulating film provided over said each information storage capacitive element and defining a third through hole in said third insulating film provided over said second interconnection; and forming a fourth conductive film over said third insulating film and patterning said fourth conductive film to thereby form a feeding interconnection layer electrically connected to the upper electrode of said each information storage capacitive element via said second through hole, and a third interconnection electrically connected to said second interconnection via said third through hole.
Claim 2
Independent Claim
315 words
A method of manufacturing a semiconductor integrated circuit device, comprising the steps of: forming memory cell selection MISFETs in a memory array region on a main surface of a semiconductor substrate and forming MISFETs for a peripheral circuit in a peripheral circuit region; forming a first interconnection over the main surface of said semiconductor substrate with the MISFETs formed therein; forming a first insulating film over said first interconnection; defining grooves in said first insulating film in said memory array region; forming a first conductive film over said first insulating film including the interior of said grooves and forming a lower electrode of an information storage capacitive element inside said each groove; forming a second conductive film over said lower electrode with a capacitive insulating film interposed therebetween, and pattering said second conductive film to thereby form each upper electrode of said information storage capacitive element; forming a second insulating film over said each information storage capacitive element; defining a first through hole in an insulating film including said second insulating film and said first insulating film placed in a layer therebelow; forming a third conductive film over said second insulating film and patterning said third conductive film to thereby form a second interconnection electrically connected to said first interconnection via said first through hole; forming a third insulating film over said second interconnection; defining a second through hole in said third insulating film provided over said each information storage capacitive element and defining a third through hole in said third insulating film provided over said second interconnection; and forming a fourth conductive film over said third insulating film and patterning said fourth conductive film to thereby form a feeding interconnection layer electrically connected to the upper electrode of said each information storage capacitive element via said second through hole, and a third interconnection electrically connected to said second interconnection via said third through hole.
Claim 3
Dependent Claim
63 words
The method according to claim 1 , wherein said step of forming the third insulating film over the second interconnection includes a step of forming an insulating film by a high-density plasma CVD method, and said step of forming the second insulating film over said information storage capacitive element excludes the step of forming the insulating film by the high-density plasma CVD method.
Claim 4
Dependent Claim
47 words
The method according to claim 2 , wherein said step of forming the insulating film by the high-density plasma CVD method is a step of forming a silicon oxide film by a high-density plasma CVD method using a source gas containing monosilane, oxygen and an inert gas.
Claim 5
Dependent Claim
60 words
The method according to claim 2 , wherein said step of forming the third insulating film over the second interconnection further includes a step of forming a fourth insulating film over the insulating film formed by the high-density plasma CVD method, and a step of flattening said fourth insulating film over the surface thereof by a chemical mechanical polishing method.
Claim 6
Dependent Claim
21 words
The method according to claim 1 , wherein said feeding interconnection and said third interconnection are formed in the same step.
Claim 7
Dependent Claim
15 words
The method according to claim 1 , wherein said first interconnection includes a bit line.
Claim 8
Independent Claim
128 words
A method of manufacturing a semiconductor integrated circuit device, comprising the steps of: forming MISFETs over a main surface of a semiconductor substrate; forming a capacitive element electrically connected to said each MISFET over said each MISFET; forming a first insulating film for surrounding a peripheral portion of said capacitive element; forming a first interconnection over said first insulating film; forming a second insulating film over said first interconnection; defining a first opening for exposing a capacitive element at the bottom of an insulating film including said second insulating film; defining a second opening for exposing said first interconnection at the bottom of the insulating film including said second insulating film; forming a first plug within said first opening; and forming a second plug within said second opening.
Claim 9
Independent Claim
128 words
A method of manufacturing a semiconductor integrated circuit device, comprising the steps of: forming MISFETs over a main surface of a semiconductor substrate; forming a capacitive element electrically connected to said each MISFET over said each MISFET; forming a first insulating film for surrounding a peripheral portion of said capacitive element; forming a first interconnection over said first insulating film; forming a second insulating film over said first interconnection; defining a first opening for exposing a capacitive element at the bottom of an insulating film including said second insulating film; defining a second opening for exposing said first interconnection at the bottom of the insulating film including said second insulating film; forming a first plug within said first opening; and forming a second plug within said second opening.
Claim 10
Dependent Claim
26 words
The method according to claim 7 , wherein said step of defining said first opening and said step of defining said second opening are simultaneously performed.
Claim 11
Dependent Claim
22 words
The method according to claim 7 , wherein the depth of said first opening is greater than that of said second opening.
Claim 12
Dependent Claim
50 words
The method according to claim 7 , further including a step of forming a first interconnection below said first insulating film, a step of defining a third opening for exposing said first interconnection in said first insulating film; and a step of forming a third plug within said third opening.
Claim 13
Dependent Claim
27 words
The method according to claim 7 , wherein the thickness of said first insulating film is substantially the same degree as the height of said capacitive element.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2004-07-09 | 2005-01-08 | 2005-07-10 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2008-07-09 | 2009-01-08 | 2009-07-10 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2012-07-09 | 2013-01-08 | 2013-07-10 | $7700.00 | Window Closed / Lapsed |