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JPH077084A Expired / Lapsed JP ⏱️ 0.0 years remaining

Semiconductor memory device and manufacturing method thereof

Assignee: Samsung Electronics Co Ltd
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Filing: 1992-07-14
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Granted: —
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Expires: 2012-07-14
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Abstract

Abstract Translated from Japanese (57)【要約】 【目的】 半導体装置及びその製造方法を提供するこ と。 【構成】 セルアレイ領域と周辺回路領域から構成され る半導体メモリ装置において、前記セルアレイ領域と周 辺回路領域の間の境界領域に、前記セルアレイ領域を囲 む形でその上部が除去された形のトンネルが形成され る。 【効果】 従来半導体メモリ装置で問題となったセルア レイ領域と周辺回路領域の間の段差による導電層の信頼 度低下を防止できるだけではなく、周辺回路領域の表面 平坦化を同時に達成できる。 (57) [Summary] [Object] To provide a semiconductor device and a manufacturing method thereof. In a semiconductor memory device including a cell array region and a peripheral circuit region, a tunnel is formed in a boundary region between the cell array region and the peripheral circuit region with the upper portion thereof being removed so as to surround the cell array region. To be done. [Effect] Not only can the reliability of the conductive layer be prevented from being lowered due to the step between the cell array region and the peripheral circuit region, which has been a problem in the conventional semiconductor memory device, but also the surface of the peripheral circuit region can be planarized at the same time.

Inventors

  • 👤 Ji-Hong Ahn
  • 👤 智弘 安

Bibliographic Details

Application Number —
Jurisdiction JP
Data Source google_patents
Last Synchronized 2026-11-09 03:12
CPC Classifications
H; H10; H10B; H10B12/00; H10B12/01; H10B12/02; H10B12/03; H10B12/033; H10B12/30; H10B12/31; H10B12/318; H10W; H10W20/00; H10W20/01; H10W20/40

Claims Analysis

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References Cited (Backward Citations)

JPH0410651A Cited

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