US6258624B1
Expired / Lapsed
US
⏱️ 0.0 years remaining
Semiconductor package having downset leadframe for reducing package bow
Assignee: Micron Technology Inc
•
Filing: 2000-05-01
•
Granted: 2001-07-10
•
Expires: 2020-05-01
Abstract
Abstract A bow resistant semiconductor package includes a semiconductor die, a leadframe segment and a plastic body. The leadframe segment includes lead fingers attached and wire bonded to the die, and opposing volume equalizing members proximate to lateral edges of the die. The volume equalizing members are downset from a first plane proximate to a face of the die, to a second plane proximate to a center line of the package. In addition, the volume equalizing members are configured to rigidify the package, and to substantially equalize the volumes of molding compound on either side of the package center line and leadframe segment. The equal volumes of molding compound reduce thermo-mechanical stresses generated during cooling of the molding compound, and reduce package bow. With reduced package bow, a planarity of the terminal leads on the package is maintained. Also, stresses on bonded connections between the terminal leads and electrodes on a supporting substrate, such as a printed circuit board, or multi chip module substrate, are reduced.
Inventors
- 👤 David J. Corisis
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 17:57
CPC Classifications
H; H10; H10W; H10W70/00; H10W70/40; H10W70/411; H10W70/415; H10W70/421; H10W70/424; H10W70/427; H10W72/00; H10W72/071; H10W72/073; H10W72/075; H10W72/07551; H10W72/07554; H10W72/50; H10W72/541; H10W72/5449; H10W72/547; H10W72/59; H10W72/851; H10W72/853; H10W72/865; H10W72/90; H10W72/931; H10W72/932; H10W72/941; H10W72/944; H10W72/9445; H10W72/951; H10W72/952; H10W74/00; H10W90/00; H10W90/701; H10W90/731; H10W90/736; H10W90/751; H10W90/756
Claims Analysis
Total Claims: 24
Claim 1
Independent Claim
74 words
A method for fabricating a semiconductor package comprising: providing a leadframe segment comprising a major surface, a plurality of lead fingers and at least one volume equalizing member downset from the major surface; providing a semiconductor die; attaching the die to the lead fingers; and molding a package body on the leadframe segment and on the die, the package body comprising substantially equal volumes of molding compound above and below the volume equalizing member.
Claim 2
Independent Claim
74 words
A method for fabricating a semiconductor package comprising: providing a leadframe segment comprising a major surface, a plurality of lead fingers and at least one volume equalizing member downset from the major surface; providing a semiconductor die; attaching the die to the lead fingers; and molding a package body on the leadframe segment and on the die, the package body comprising substantially equal volumes of molding compound above and below the volume equalizing member.
Claim 3
Dependent Claim
26 words
The method of claim 1 wherein the volume equalizing member comprises opposing paddles extending from lateral edges of the package to lateral edges of the die.
Claim 4
Dependent Claim
21 words
The method of claim 1 wherein the volume equalizing member comprises at least one downset lead finger on the leadframe segment.
Claim 5
Dependent Claim
23 words
The method of claim 1 wherein the volume equalizing member comprises at least one downset and upset lead finger on the leadframe segment.
Claim 6
Independent Claim
111 words
A method for fabricating a semiconductor package comprising: providing a semiconductor die comprising a face and a plurality of bond pads on the face; providing a leadframe segment comprising a plurality of lead fingers, and a pair of opposing volume equalizing member downset from a first plane proximate to the face to a second plane proximate to a center line of the package; providing a semiconductor die; attaching the die to the lead fingers; wire bonding the die to the lead fingers; and molding a package body on the leadframe segment and on the die, the package body comprising substantially equal volumes of molding compound above and below the center line.
Claim 7
Independent Claim
111 words
A method for fabricating a semiconductor package comprising: providing a semiconductor die comprising a face and a plurality of bond pads on the face; providing a leadframe segment comprising a plurality of lead fingers, and a pair of opposing volume equalizing member downset from a first plane proximate to the face to a second plane proximate to a center line of the package; providing a semiconductor die; attaching the die to the lead fingers; wire bonding the die to the lead fingers; and molding a package body on the leadframe segment and on the die, the package body comprising substantially equal volumes of molding compound above and below the center line.
Claim 8
Dependent Claim
16 words
The method of claim 5 wherein the leadframe segment and the die have a lead-on-chip configuration.
Claim 9
Dependent Claim
23 words
The method of claim 5 wherein at least one of the lead fingers is downset from the first plane to the second plane.
Claim 10
Dependent Claim
33 words
The method of claim 5 wherein at least one of the lead fingers is downset from the first plane to the second plane and upset from the second plane to the first plane.
Claim 11
Dependent Claim
15 words
The method of claim 5 wherein the package comprises a thin small outline package (TSOP).
Claim 12
Independent Claim
102 words
A method for fabricating a semiconductor package comprising: providing a semiconductor die comprising a face and opposing lateral edges; providing a leadframe segment comprising a plurality of lead fingers and opposing paddles downset from a plane of the lead fingers to a second plane; attaching the face to the lead fingers with the paddles located proximate to the lateral edges of the die; and molding a package body on the leadframe segment and on the die, the package body having a center line proximate to the second plane and comprising substantially equal volumes of molding compound above and below the center line.
Claim 13
Independent Claim
102 words
A method for fabricating a semiconductor package comprising: providing a semiconductor die comprising a face and opposing lateral edges; providing a leadframe segment comprising a plurality of lead fingers and opposing paddles downset from a plane of the lead fingers to a second plane; attaching the face to the lead fingers with the paddles located proximate to the lateral edges of the die; and molding a package body on the leadframe segment and on the die, the package body having a center line proximate to the second plane and comprising substantially equal volumes of molding compound above and below the center line.
Claim 14
Dependent Claim
25 words
The method of claim 10 further comprising providing the leadframe segment with at least one lead finger downset from the plane to the second plane.
Claim 15
Dependent Claim
34 words
The method of claim 10 further comprising providing the leadframe segment with at least one lead finger downset from the plane to the second plane, and upset from the second plane to the plane.
Claim 16
Dependent Claim
19 words
The method of claim 10 further comprising wire bonding the die to at least one of the lead fingers.
Claim 17
Dependent Claim
16 words
The method of claim 10 wherein the plane comprises a major surface of the leadframe segment.
Claim 18
Dependent Claim
23 words
The method of claim 10 wherein the paddles extend from lateral edges of the package body to the lateral edges of the die.
Claim 19
Independent Claim
121 words
A method for fabricating a semiconductor package comprising: providing a semiconductor die comprising a face and a plurality of bond pads on the face; providing a leadframe segment comprising a plurality of lead fingers and opposing volume equalizing members downset from a plane of the lead fingers to a second plane; wire bonding the bond pads to the lead fingers with the paddles located proximate to the lateral edges of the die; and molding a molding compound on the leadframe segment and on the die to form a package body, with the opposing volume equalizing members rigidifying the package body and occupying a space selected to substantially equalize a volume of the molding compound on either side of the leadframe segment.
Claim 20
Independent Claim
121 words
A method for fabricating a semiconductor package comprising: providing a semiconductor die comprising a face and a plurality of bond pads on the face; providing a leadframe segment comprising a plurality of lead fingers and opposing volume equalizing members downset from a plane of the lead fingers to a second plane; wire bonding the bond pads to the lead fingers with the paddles located proximate to the lateral edges of the die; and molding a molding compound on the leadframe segment and on the die to form a package body, with the opposing volume equalizing members rigidifying the package body and occupying a space selected to substantially equalize a volume of the molding compound on either side of the leadframe segment.
Claim 21
Dependent Claim
24 words
The method of claim 16 further comprising attaching the die to at least some of the lead fingers prior to the wire bonding step.
Claim 22
Dependent Claim
20 words
The method of claim 16 wherein the second plane is located proximate to a center line of the package body.
Claim 23
Dependent Claim
16 words
The method of claim 16 wherein the members are located on either side of the die.
Claim 24
Dependent Claim
31 words
The method of claim 16 wherein the members are located on either side of the die and extend from lateral edges of the die to lateral edges of the package body.
References Cited (Backward Citations)
US5214307A
Cited
US5767572A
Cited
US5442231A
Cited
US5291059A
Cited
US5767560A
Cited
US5220195A
Cited
US5637915A
Cited
US5437915A
Cited
US5365107A
Cited
US5638596A
Cited
USRE36613E
Cited
US5998866A
Cited
US5498901A
Cited
US5814877A
Cited
US5594234A
Cited
US5905299A
Cited
US5770479A
Cited
US6068180A
Cited
US6043430A
Cited
US5920114A
Cited
US6049125A
Cited
US6002165A
Cited
US6075283A
Cited
US6078099A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2004-07-09 | 2005-01-08 | 2005-07-10 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2008-07-09 | 2009-01-08 | 2009-07-10 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2012-07-09 | 2013-01-08 | 2013-07-10 | $7700.00 | Window Closed / Lapsed |