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US6256247B1
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Differential sense amplifiers for resistive cross point memory cell arrays
Assignee: Samsung Electronics Co Ltd
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Filing: 2000-12-19
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Granted: 2001-07-03
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Expires: 2020-12-19
Abstract
Abstract Resistance of a memory cell element in a resistive cross point memory cell array is sensed by a read circuit including a differential amplifier, a first direct injection preamplifier and a second direct injection preamplifier. During a read operation, the first direct injection preamplifier is coupled to a first input node of the differential amplifier, and the second direct injection preamplifier is coupled to a second input node of the differential amplifier.
Inventors
- 👤 Frederick A. Perner
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 16:00
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/02; G11C11/14; G11C11/15; G11C11/16; G11C11/165; G11C11/1673; G11C27/00; G11C27/02
Claims Analysis
Total Claims: 25
Claim 1
Independent Claim
63 words
A read circuit for an information storage device, the information storage device including a resistive cross point memory cell array, the circuit comprising: a differential amplifier having first and second input nodes; a first direct injection preamplifier coupled to the first input node of the differential amplifier; and a second direct injection preamplifier coupled to the second input node of the differential amplifier.
Claim 2
Dependent Claim
63 words
A read circuit for an information storage device, the information storage device including a resistive cross point memory cell array, the circuit comprising: a differential amplifier having first and second input nodes; a first direct injection preamplifier coupled to the first input node of the differential amplifier; and a second direct injection preamplifier coupled to the second input node of the differential amplifier.
Claim 3
Dependent Claim
15 words
The circuit of claim 1 , wherein the first and second preamplifiers are autocalibration types.
Claim 4
Dependent Claim
16 words
The circuit of claim 1 , wherein the differential amplifier is a current mode differential amplifier.
Claim 5
Dependent Claim
59 words
The circuit of claim 3 , wherein the differential amplifier includes a current mirror circuit, the current mirror circuit including a mirror transistor coupled to the first input node and a reference transistor coupled to the second input node; and wherein the read circuit further comprises a comparator for comparing signals at the input nodes of the differential amplifier.
Claim 6
Dependent Claim
31 words
The circuit of claim 4 , wherein during a read operation the comparator compares a current flowing through a selected memory cell element to a current flowing through a reference element.
Claim 7
Dependent Claim
29 words
The circuit of claim 4 , wherein during a read operation the comparator compares a voltage at the first input node to a voltage at the second input node.
Claim 8
Dependent Claim
48 words
The circuit of claim 1 , further comprising means for coupling the first preamplifier between the first input node and a selected memory cell element during read operations and for coupling the second preamplifier between the second input node and a reference memory cell element during read operations.
Claim 9
Dependent Claim
19 words
The circuit of claim 1 , further comprising means for applying equipotential isolation to the array during read operations.
Claim 10
Dependent Claim
97 words
An information storage device comprising: a resistive cross point array of memory cell elements; and a read circuit including a plurality of differential amplifiers, a plurality of first direct injection preamplifiers, and a plurality of second direct injection preamplifiers; at least one of the first preamplifiers being coupled between a first memory cell element of the array and a first differential amplifier input node during a read operation; at least one of the second preamplifiers being coupled between a second memory cell element of the array and a second differential amplifier input node during the read operation.
Claim 11
Dependent Claim
97 words
An information storage device comprising: a resistive cross point array of memory cell elements; and a read circuit including a plurality of differential amplifiers, a plurality of first direct injection preamplifiers, and a plurality of second direct injection preamplifiers; at least one of the first preamplifiers being coupled between a first memory cell element of the array and a first differential amplifier input node during a read operation; at least one of the second preamplifiers being coupled between a second memory cell element of the array and a second differential amplifier input node during the read operation.
Claim 12
Dependent Claim
50 words
The device of claim 9 , further comprising a plurality of traces crossing the memory cell elements, wherein a potential is applied to the trace connected to the selected memory cell element; and wherein an equal potential is applied to a subset of traces connected to unselected memory cell elements.
Claim 13
Dependent Claim
19 words
The device of claim 9 , wherein data is stored in the memory cell elements in a bar-bitbar manner.
Claim 14
Dependent Claim
15 words
The device of claim 9 , wherein the first and second preamplifiers are autocalibration types.
Claim 15
Dependent Claim
15 words
The device of claim 9 , wherein the differential amplifiers are current mode differential amplifiers.
Claim 16
Dependent Claim
30 words
The device of claim 9 , wherein during said read operation each differential amplifier amplifies a difference in currents flowing through a selected memory cell element and a reference element.
Claim 17
Dependent Claim
23 words
The device of claim 9 , wherein during said read operation each differential amplifier amplifies a difference in voltage at its input nodes.
Claim 18
Independent Claim
97 words
A method of using a differential amplifier, first and second direct injection preamplifiers, and a reference element to sense a resistance state of a memory cell element in a resistive cross point memory cell array, the differential amplifier having first and second input nodes, the method comprising: coupling the first direct injection preamplifier between the memory cell element and the first input node of the differential amplifier; coupling the second direct injection preamplifier between the reference element and the second input node of the differential amplifier; and comparing signals at the inputs nodes of the differential amplifier.
Claim 19
Independent Claim
97 words
A method of using a differential amplifier, first and second direct injection preamplifiers, and a reference element to sense a resistance state of a memory cell element in a resistive cross point memory cell array, the differential amplifier having first and second input nodes, the method comprising: coupling the first direct injection preamplifier between the memory cell element and the first input node of the differential amplifier; coupling the second direct injection preamplifier between the reference element and the second input node of the differential amplifier; and comparing signals at the inputs nodes of the differential amplifier.
Claim 20
Dependent Claim
18 words
The method of claim 16 , further comprising waiting a time interval before storing results of the comparison.
Claim 21
Dependent Claim
22 words
The method of claim 16 , further comprising applying equipotential isolation to the array while comparing the signals at the input nodes.
Claim 22
Dependent Claim
14 words
The method of claim 16 , wherein the sensing is performed in current mode.
Claim 23
Dependent Claim
14 words
The method of claim 16 , wherein the sensing is performed in voltage mode.
Claim 24
Dependent Claim
11 words
The method of claim 16 , further comprising autocalibrating the preamplifiers.
Claim 25
Dependent Claim
28 words
The method of claim 16 , further comprising storing a data value in the memory cell element and a complement of the data value in the reference element.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2004-07-02 | 2005-01-01 | 2005-07-03 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2008-07-02 | 2009-01-01 | 2009-07-03 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2012-07-02 | 2013-01-01 | 2013-07-03 | $7700.00 | Window Closed / Lapsed |