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US6255167B1
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Method of forming high density buried bit line flash EEPROM memory cell with a shallow trench floating gate
Assignee: Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Filing: 1999-06-04
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Granted: 2001-07-03
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Expires: 2019-06-04
Abstract
Abstract A method of fabricating buried bit line flash EEROM cells with shallow trench floating gates for suppressing the short channel effect is disclosed. The method includes the following steps. First, a first polysilicon layer with conductive impurities and a nitride capping layer are sequentially formed on a silicon substrate. The nitride cap layer serves as an anti-reflection coating (ARC) layer for improving the resolution of lithography. Then a photo-mask pattern on the ARC layer is formed to define trench regions, an anisotropic etching is performed to etch away unmasked portions of the nitride cap layer through the first polysilicon layer and slightly recess the silicon substrate using the patterned mask as a mask. After removing the patterned mask, a thermal annealed process is performed to grow a polyoxide layer on the sidewall of the first polysilicon layer and an thin oxynitride layer on the surface of the recessed silicon substrate. In the meantime, the buried bit lines are formed where each bit line is a layer beneath the first polysilicon layer. The trenches are then refilled with a silicon layer. A planarization process then follows. Subsequently, an interpoly dielectric layer is formed. Finally, a second polysilicon layer is formed and pattered to define word lines.
Inventors
- 👤 Shye-Lin Wu
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 08:37
CPC Classifications
H; H10; H10B; H10B69/00; H10B41/00; H10B41/30
Claims Analysis
Total Claims: 14
Claim 1
Independent Claim
224 words
A method of fabricating buried bit line flash EEPROM cells, each with a trench floating gate, comprising the step sequence of: forming a first polysilicon layer with conductive impurities on a silicon substrate; forming a nitride capping layer on said first polysilicon layer; coating a patterned mask on said nitride capping layer to define a plurality of buried bit line regions, said nitride capping layer being serves as an antireflection coating layer; forming a plurality of trenches by performing an anisotropic etching to etch away unmask portions of said nitride capping layer through said first polysilicon layer and, recessing said silicon substrate using said patterned mask as a mask; removing said patterned masks; concurrently thermal growing a polyoxide layer on each sidewall of said first polysilicon layer and a gate dielectric layer on each surface of said recessed silicon substrate and forming buried bit lines using said conductive impurities in remnant portions of said first polysilicon layer as a diffusion source; forming a silicon layer to refill said plurality of trenches; performing a planarization process to said silicon layer so as to form a plain surface using said nitride capping layer as an etching stopping layer; forming an interpoly dielectric layer on all areas; forming a second polysilicon layer on said interpoly dielectric layer; and forming word lines by patterning said second polysilicon layer.
Claim 2
Independent Claim
224 words
A method of fabricating buried bit line flash EEPROM cells, each with a trench floating gate, comprising the step sequence of: forming a first polysilicon layer with conductive impurities on a silicon substrate; forming a nitride capping layer on said first polysilicon layer; coating a patterned mask on said nitride capping layer to define a plurality of buried bit line regions, said nitride capping layer being serves as an antireflection coating layer; forming a plurality of trenches by performing an anisotropic etching to etch away unmask portions of said nitride capping layer through said first polysilicon layer and, recessing said silicon substrate using said patterned mask as a mask; removing said patterned masks; concurrently thermal growing a polyoxide layer on each sidewall of said first polysilicon layer and a gate dielectric layer on each surface of said recessed silicon substrate and forming buried bit lines using said conductive impurities in remnant portions of said first polysilicon layer as a diffusion source; forming a silicon layer to refill said plurality of trenches; performing a planarization process to said silicon layer so as to form a plain surface using said nitride capping layer as an etching stopping layer; forming an interpoly dielectric layer on all areas; forming a second polysilicon layer on said interpoly dielectric layer; and forming word lines by patterning said second polysilicon layer.
Claim 3
Dependent Claim
35 words
The method of claim 1 , wherein said step of forming a first polysilicon layer with conductive impurities is formed at a temperature of about 400-625° C. to about a thickness of about 10-100 nm.
Claim 4
Dependent Claim
43 words
The method of claim 1 , wherein said first polysilicon layer is formed by a method selected from the group consisting of a in-situ doped CVD process, CVD process followed by a pocl doped process, and a CVD process followed by ion implant.
Claim 5
Dependent Claim
20 words
The method of claim 1 , wherein said nitride capping layer is implemented at a temperature of about 400-800° C.
Claim 6
Dependent Claim
23 words
The method of claim 1 , wherein said gate dielectric layer is an oxynitride layer with a thickness of about 2-30 nm formed.
Claim 7
Dependent Claim
27 words
The method of claim 1 , wherein said step of concurrently thermal growing is done at a temperature about 700-1150° C. in an ambient N 2 O/NO.
Claim 8
Dependent Claim
38 words
The method of claim 1 , wherein said plurality of trenches are with a depth of about 3-100 nm each, said depth is measured from the upper surface of said silicon substrate to the bottom of said trench.
Claim 9
Dependent Claim
41 words
The method of claim 1 , wherein said silicon layer comprises a material selected from the group consisting of amorphous silicon and polysilicon, and said silicon layer contains n-type impurities to concentrations of about 5×10 19 -5×10 21 /cm 3 .
Claim 10
Dependent Claim
22 words
The method of claim 1 , wherein said steps of forming silicon layer is done at a temperature of about 450-650° C.
Claim 11
Dependent Claim
20 words
The method of claim 1 , wherein said step of performing a planarization process is done by a CMP process.
Claim 12
Dependent Claim
40 words
The method of claim 1 , wherein said interpoly dielectric layer is a stacked ONO layer, said ONO is with a second oxide layer over a nitride layer/first oxide layer to about 1-5 nm, 4-20 nm, and 1-5 nm, respectively.
Claim 13
Dependent Claim
40 words
The method of claim 1 , wherein said step of forming polysilicon layer is performed by a LPCVD method at a temperature of about 450-650° C., and with n-type doping concentrations of about 5×10 19 -5×10 21 /cm 3 .
Claim 14
Dependent Claim
24 words
The method of claim 1 , wherein said conductive impurities are selected from the group consisting of arsenic containing dopants and phosphorus containing dopants.
References Cited (Backward Citations)
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