US5529943A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method of making buried bit line ROM with low bit line resistance
Assignee: United Microelectronics Corp
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Filing: 1994-09-30
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Granted: 1996-06-25
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Expires: 2014-09-30
Abstract
Abstract A ROM array comprises orthogal sets of buried bit lines and polysilicon wordlines. The buried bit lines comprise trenches with insulating material on the side walls, the trenches then being filled with polysilicon. This reduces bit line sheet resistance and increases the punch-through voltage between adjacent bit lines.
Inventors
- 👤 Gary Hong
- 👤 Chen C. Hsue
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 10:30
CPC Classifications
H; H10; H10B; H10B20/00; H10B20/27; H10B20/30; H10B20/38
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
107 words
A method for forming a buried bit line for a memory array, comprising the steps of: (a) forming a trench having side walls in a semiconductor substrate of a first conductivity type; (b) depositing dielectric material in the trench; (c) removing a portion of the dielectric material so a top portion of the trench side walls is exposed; and (d) creating a dopant source, having an opposite conductivity of the first conductivity type, in the trench for contacting the exposed portion of the sidewall; and (e) diffusing dopant from the dopant source into the substrate through the exposed top portion of the sidewall to form a bitline.
Claim 2
Independent Claim
107 words
A method for forming a buried bit line for a memory array, comprising the steps of: (a) forming a trench having side walls in a semiconductor substrate of a first conductivity type; (b) depositing dielectric material in the trench; (c) removing a portion of the dielectric material so a top portion of the trench side walls is exposed; and (d) creating a dopant source, having an opposite conductivity of the first conductivity type, in the trench for contacting the exposed portion of the sidewall; and (e) diffusing dopant from the dopant source into the substrate through the exposed top portion of the sidewall to form a bitline.
Claim 3
Dependent Claim
23 words
The method of claim 1, further comprising the step of: depositing an oxide layer and a polysilicon layer on top of the trench.
Claim 4
Dependent Claim
49 words
The method of claim 1, further comprising the steps of: (a) after depositing a dielectric material in the trench, partially filling the trench to a predetermined level with SOG; and (b) the step of removing a portion of the dielectric material includes exposing the sidewalls above said predetermined level.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-06-25 | 1999-12-25 | 2000-06-25 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-06-25 | 2003-12-25 | 2004-06-25 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-06-25 | 2007-12-25 | 2008-06-25 | $7700.00 | Window Closed / Lapsed |