← Back to Patent Explorer
US5429973A Expired / Lapsed US ⏱️ 0.0 years remaining

Trench buried-bit line mask ROM process

Assignee: United Microelectronics Corp
•
Filing: 1994-02-02
•
Granted: 1995-07-04
•
Expires: 2014-02-02
📄 Original PDF 🌐 Google Patents 🔄 Sync Now

Abstract

Abstract A method for fabricating a trench buried-bit line mask ROM includes the steps: firstly, longitudinally coating a plurality of spaced photo-resist strips on a silicon well surface thus dividing the silicon well surface into a plurality longitudinally spaced strip regions; secondly, etching into each of the silicon strip regions a predetermined depth and forming a longitudinal trench therein; thirdly, depositing a strip of N+ ions along each of the longitudinal trenches such that each strip of N+ ions constitutes a bit line of the ROM; fourthly, removing the photoresist strips from the silicon well surface and leaving a silicon ridge between each two trenches such that an inverse U-shaped channel is defined substantially along periphery of each silicon ridge; fifthly, applying a layer of oxide material to cover the trenches and the silicon ridges; and, sixthly, laterally depositing a plurality of spaced semiconductor strips on the oxide layer such that each of the lateral semiconductor strips constitutes a word line of the ROM.

Inventors

  • 👤 Gary Hong

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-31 00:45
CPC Classifications
H; H10; H10B; H10B20/00; H10B20/27; H10B20/30; H10B20/38; H10B20/383; Y; Y10; Y10S; Y10S148/00; Y10S148/05

Claims Analysis

Total Claims: 6
Claim 1
Independent Claim 156 words
A method for fabricating a trench buried-bit line mask ROM comprising the steps of: firstly, longitudinally coating a plurality of spaced photoresist strips on a silicon well surface thus dividing said silicon well surface into a plurality of longitudinally spaced silicon strip regions; secondly, etching into said silicon strip regions and forming a longitudinal trench in each of said silicon strip regions; thirdly, applying an ion implantation process on the trench thus forming a bit line of said ROM; fourthly, removing said photoresist strips from said silicon well surface and leaving a silicon ridge between every two adjacent trenches such that an inverse U-shaped channel is formed along a periphery of said silicon ridge; fifthly, applying a layer of oxide material to cover the trenches and the silicon ridges; and sixthly, laterally depositing a plurality of spaced semiconductor strips on said oxide layer such that said lateral semiconductor strips constitute a word line of said ROM.
Claim 2
Independent Claim 156 words
A method for fabricating a trench buried-bit line mask ROM comprising the steps of: firstly, longitudinally coating a plurality of spaced photoresist strips on a silicon well surface thus dividing said silicon well surface into a plurality of longitudinally spaced silicon strip regions; secondly, etching into said silicon strip regions and forming a longitudinal trench in each of said silicon strip regions; thirdly, applying an ion implantation process on the trench thus forming a bit line of said ROM; fourthly, removing said photoresist strips from said silicon well surface and leaving a silicon ridge between every two adjacent trenches such that an inverse U-shaped channel is formed along a periphery of said silicon ridge; fifthly, applying a layer of oxide material to cover the trenches and the silicon ridges; and sixthly, laterally depositing a plurality of spaced semiconductor strips on said oxide layer such that said lateral semiconductor strips constitute a word line of said ROM.
Claim 3
Dependent Claim 26 words
A method for fabricating a trench buried-bit line mask ROM as claimed in claim 1, wherein the etching depth for said trench is about 5000 Å.
Claim 4
Dependent Claim 22 words
A method for fabricating a trench buried-bit line mask ROM as claimed in claim 1, wherein said lateral semiconductor strips comprise polysilicon.
Claim 5
Dependent Claim 23 words
A method for fabricating a trench buried-bit line mask ROM as claimed in claim 1, wherein said lateral semiconductor strips comprise tungsten silicide.
Claim 6
Dependent Claim 23 words
A method for fabricating a trench buried-bit line mask ROM as claimed in claim 1, wherein said lateral semiconductor strips comprise molybdenum silicide.

References Cited (Backward Citations)

US5084418A Cited
US5021355A Cited
US5180680A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1998-07-03 1999-01-02 1999-07-04 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 2002-07-03 2003-01-02 2003-07-04 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2006-07-03 2007-01-02 2007-07-04 $7700.00 Window Closed / Lapsed

Assigned Categories & Tags

No categories assigned to this patent yet.

Assign Category Tag