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US6252807B1
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US
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Memory device with reduced power consumption when byte-unit accessed
Assignee: Renesas Electronics Corp
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Filing: 1999-12-09
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Granted: 2001-06-26
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Expires: 2019-12-09
Abstract
Abstract A memory device is arranged in such a manner that an access-target memory cell is selected from a plurality of memory cells in accordance with the level of the byte-enable signal at the timing when the level of the corresponding row address strobe signal (/RAS signal) changes, and by this arrangement, the problem resided in the conventional memory device that it could not be decided as to whether a memory block in the DRAM core was to be a selected or non-selected byte until the fall of the corresponding column address strobe signal (/CAS signal), and thus the column decoder and the preamplifier that start operating at the fall of the /RAS signal could not be efficiently controlled is solved, and due to this, electric power that might otherwise be consumed at the time of executing a byte-unit access to the wide-bus DRAM can be reduced.
Inventors
- 👤 Tomoaki Suzuki
- 👤 Haruko Sonpachi
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 14:18
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/4063; G11C11/407; G11C11/408; G11C11/4087; G11C11/4076; G11C8/00; G11C8/18
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
82 words
A memory device comprising: a plurality of memory cells configuring a DRAM, a selection means for selecting one access-target memory cell out of said plurality of memory cells in accordance with a level of a byte-enable signal when a level of a row address strobe signal changes, a reading means for reading byte-unit data from the access-target memory cell selected by said selection means, and a writing means for writing byte-unit data into the access-target memory cell selected by said selection means.
Claim 2
Dependent Claim
82 words
A memory device comprising: a plurality of memory cells configuring a DRAM, a selection means for selecting one access-target memory cell out of said plurality of memory cells in accordance with a level of a byte-enable signal when a level of a row address strobe signal changes, a reading means for reading byte-unit data from the access-target memory cell selected by said selection means, and a writing means for writing byte-unit data into the access-target memory cell selected by said selection means.
Claim 3
Dependent Claim
81 words
A memory device according to claim 1 , wherein when the level of the byte-enable signal associated with an arbitrary memory cell is in a “L” level at a fall of the row address strobe signal, said selection means eliminates the memory cell from being an access-target memory cell, whereas when the level of the byte-enable signal associated with an arbitrary memory cell is in a “H” level, said selection means determines the memory cell to be an access-target memory cell.
Claim 4
Dependent Claim
32 words
A memory device according to claim 2 , wherein said selection means inactivates reading means and writing means which are connected with the memory cell eliminated from being an access-target memory cell.
Claim 5
Dependent Claim
91 words
A memory device comprising: a plurality of memory cells configuring a DRAM, a selection means for selecting one access-target memory cell out of said plurality of memory cells in accordance with a level of a byte-enable signal when a level of a row address strobe signal and a level of a column address strobe signal change, a reading means for reading byte-unit data from the access-target memory cell selected by a selection means, and a writing means for writing byte-unit data into the access-target memory cell selected by said selection means.
Claim 6
Dependent Claim
91 words
A memory device comprising: a plurality of memory cells configuring a DRAM, a selection means for selecting one access-target memory cell out of said plurality of memory cells in accordance with a level of a byte-enable signal when a level of a row address strobe signal and a level of a column address strobe signal change, a reading means for reading byte-unit data from the access-target memory cell selected by a selection means, and a writing means for writing byte-unit data into the access-target memory cell selected by said selection means.
Claim 7
Dependent Claim
60 words
A memory device according to claim 4 , wherein said selection means determines an arbitrary memory cell to be an access target memory cell, only when the level of the byte-enable signal associated with said arbitrary memory cell is in a “H” level at a fall of the row address strobe signal and that of the column address strobe signal.
Claim 8
Dependent Claim
33 words
A memory device according to claim 5 , wherein said selection means inactivates reading means and the writing means which are connected with a memory cell eliminated from being an access-target memory cell.
Claim 9
Dependent Claim
62 words
A memory device according to claim 6 , wherein even when the byte-enable signal is in the “H” level at the fall of the row address strobe signal, if the byte-enable signal is in a “L” level at a fall of the column address strobe signal, said selection means inactivates only some particular elements configuring the reading means and the writing means.
Claim 10
Dependent Claim
23 words
A memory device according to claim 4 further comprising a decode means for generating the byte-enable signal in accordance with an address signal.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2004-06-25 | 2004-12-25 | 2005-06-26 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2008-06-25 | 2008-12-25 | 2009-06-26 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2012-06-25 | 2012-12-25 | 2013-06-26 | $7700.00 | Window Closed / Lapsed |