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US6239010B1 Expired / Lapsed US ⏱️ 0.0 years remaining

Method for manually manufacturing capacitor

Assignee: United Microelectronics Corp
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Filing: 1999-07-02
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Granted: 2001-05-29
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Expires: 2019-07-02
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Abstract

Abstract A method for manufacturing a capacitor of a mixed-mode circuit. A substrate is provided. An isolation region is formed on the substrate to define an active region in the substrate. An oxide layer, a first polysilicon layer and a first silicide layer are formed over the substrate. The oxide layer, the first polysilicon layer and the first silicon layer are patterned to form a gate structure on the active region and to form a first polysilicon electrode and a first silicide electrode on the isolation region. A dielectric layer is formed over the substrate. An opening is formed to expose a portion of the first silicide electrode. A second silicide layer is formed on a sidewall and a bottom of the opening and on the dielectric layer. A planarization process is performed to remove a portion of the second silicide layer above the dielectric layer, wherein the remaining second silicide layer in the opening, the silicide electrode and the polysilicon electrode together form a bottom electrode of the capacitor. A capacitor dielectric layer is formed over the substrate. A first metal layer is formed over the substrate. The first metal layer is patterned to form an upper electrode of the capacitor.

Inventors

  • 👤 Jau-Hone Lu

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-11-09 03:06
CPC Classifications
H; H10; H10D; H10D1/00; H10D1/60; H10D1/68; H10D1/692; H10D1/696; H10P; H10P52/00; H10P52/40; H10P52/403; H10W; H10W20/00; H10W20/01; H10W20/031

Claims Analysis

Total Claims: 22
Claim 1
Independent Claim 194 words
A method of manufacturing a capacitor for a mixed-mode circuit, comprising the steps of: providing a substrate; forming an isolation region on the substrate to define an active region in the substrate; forming an oxide layer, a first polysilicon layer and a first silicide layer over the substrate; patterning the oxide layer, the first polysilicon layer and the first silicide layer to form a gate structure on the active region and to form a first polysilicon electrode and a first silicide electrode on the isolation region; forming a dielectric layer over the substrate; forming an opening exposing a portion of the first silicide electrode; forming a second silicide layer on a sidewall and a bottom of the opening and on the dielectric layer; performing a planarization process to remove a portion of the second silicide layer above the dielectric layer, wherein the remaining second silicide layer in the opening, the silicide electrode and the polysilicon electrode together form a bottom electrode of the capacitor; forming a capacitor dielectric layer over the substrate; forming a first metal layer over the substrate; and patterning the first metal layer to form an upper electrode of the capacitor.
Claim 2
Independent Claim 194 words
A method of manufacturing a capacitor for a mixed-mode circuit, comprising the steps of: providing a substrate; forming an isolation region on the substrate to define an active region in the substrate; forming an oxide layer, a first polysilicon layer and a first silicide layer over the substrate; patterning the oxide layer, the first polysilicon layer and the first silicide layer to form a gate structure on the active region and to form a first polysilicon electrode and a first silicide electrode on the isolation region; forming a dielectric layer over the substrate; forming an opening exposing a portion of the first silicide electrode; forming a second silicide layer on a sidewall and a bottom of the opening and on the dielectric layer; performing a planarization process to remove a portion of the second silicide layer above the dielectric layer, wherein the remaining second silicide layer in the opening, the silicide electrode and the polysilicon electrode together form a bottom electrode of the capacitor; forming a capacitor dielectric layer over the substrate; forming a first metal layer over the substrate; and patterning the first metal layer to form an upper electrode of the capacitor.
Claim 3
Dependent Claim 36 words
The method of claim 1 , wherein before the step of forming the first metal layer, further comprises forming a contact hole and forming a second metal layer to cover the opening and the contact hole.
Claim 4
Dependent Claim 50 words
The method of claim 2 , wherein after the step of forming the second metal layer, further comprises steps of: forming a third metal layer over the substrate; and removing a portion of the third metal layer above the dielectric layer to form a contact plug in the contact hole.
Claim 5
Dependent Claim 65 words
The method of claim 3 , wherein after the step of forming the third metal layer, further comprises steps of: forming a fourth metal layer over the substrate; and patterning the fourth metal layer, the second metal layer and the first metal layer to form a wire electrically coupled to the contact plug and to form a part of the upper electrode of the capacitor.
Claim 6
Dependent Claim 21 words
The method of claim 3 , wherein the step of removing the portion of the third metal layer includes chemical-mechanical polishing.
Claim 7
Dependent Claim 21 words
The method of claim 3 , wherein the step of removing the portion of the third metal layer includes etching back.
Claim 8
Dependent Claim 31 words
The method of claim 3 , wherein the first metal layer and the second metal layer can be titanium/titanium nitride layers and the third metal layer can be a tungsten layer.
Claim 9
Dependent Claim 13 words
The method of claim 3 , wherein the planarization process includes chemical-mechanical polishing.
Claim 10
Dependent Claim 13 words
The method of claim 1 , wherein the planarization process includes chemical-mechanical polishing.
Claim 11
Dependent Claim 17 words
The method of claim 1 , wherein the first metal layer can be a titanium/titanium nitride layer.
Claim 12
Independent Claim 148 words
A method of manufacturing a capacitor for a mixed-mode circuit, comprising the steps of: providing a substrate; forming a first metal layer on the substrate; patterning the first metal layer to form a first wire and a first bottom electrode; forming a dielectric layer over the substrate; forming an opening exposing a portion of the first bottom electrode; forming a second metal layer on a sidewall and a bottom of the opening and on the dielectric layer; performing a planarization process to remove a portion of the second metal layer above the dielectric layer, wherein the remaining second metal layer in the opening and the first bottom electrode together form a second bottom electrode of the capacitor; forming a capacitor dielectric layer over the substrate; forming a third metal layer over the substrate; and patterning the third metal layer to form a first upper electrode of the capacitor.
Claim 13
Independent Claim 148 words
A method of manufacturing a capacitor for a mixed-mode circuit, comprising the steps of: providing a substrate; forming a first metal layer on the substrate; patterning the first metal layer to form a first wire and a first bottom electrode; forming a dielectric layer over the substrate; forming an opening exposing a portion of the first bottom electrode; forming a second metal layer on a sidewall and a bottom of the opening and on the dielectric layer; performing a planarization process to remove a portion of the second metal layer above the dielectric layer, wherein the remaining second metal layer in the opening and the first bottom electrode together form a second bottom electrode of the capacitor; forming a capacitor dielectric layer over the substrate; forming a third metal layer over the substrate; and patterning the third metal layer to form a first upper electrode of the capacitor.
Claim 14
Dependent Claim 36 words
The method of claim 11 , wherein before the step of forming the third metal layer, further comprises forming a via hole and forming a fourth metal layer to cover the opening and the via hole.
Claim 15
Dependent Claim 50 words
The method of claim 12 , further comprising after the step of forming the fourth metal layer, the steps of: forming a fifth metal layer over the substrate; and removing a portion of the fifth metal layer above the dielectric layer to form a via plug in the via hole.
Claim 16
Dependent Claim 64 words
The method of claim 13 , wherein after the step of forming the fifth metal layer, further comprises steps of: forming a sixth metal layer over the substrate; and patterning the sixth metal layer, the third metal layer and the fourth metal layer to form a second wire electrically coupled to the via plug and to form a second upper electrode of the capacitor.
Claim 17
Dependent Claim 13 words
The method of claim 13 , wherein the planarization process includes chemical-mechanical polishing.
Claim 18
Dependent Claim 21 words
The method of claim 13 , wherein the step of removing the portion of the fifth metal layer includes chemical-mechanical polishing.
Claim 19
Dependent Claim 21 words
The method of claim 13 , wherein the step of removing the portion of the fifth metal layer includes etching back.
Claim 20
Dependent Claim 39 words
The method of claim 13 , wherein the first metal layer, the second metal layer, the third metal layer and the fourth metal layer can be titanium/titanium nitride layers and the fifth metal layer can be a tungsten layer.
Claim 21
Dependent Claim 13 words
The method of claim 11 , wherein the planarization process includes chemical-mechanical polishing.
Claim 22
Dependent Claim 25 words
The method of claim 11 , wherein the first metal layer, the second metal layer and the third metal layer can be titanium/titanium nitride layers.

References Cited (Backward Citations)

US5079670A Cited
US6066528A Cited
US6096619A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 2004-05-28 2004-11-27 2005-05-29 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 2008-05-28 2008-11-27 2009-05-29 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2012-05-28 2012-11-27 2013-05-29 $7700.00 Window Closed / Lapsed

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