Patent US6236599B1 successfully refreshed from Google Patents.
US6236599B1
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Repair signal generating circuit
Assignee: Renesas Electronics Corp
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Filing: 2000-07-06
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Granted: 2001-05-22
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Expires: 2020-07-06
Abstract
Abstract In a repair signal generating circuit, a first p-channel transistor has its source connected to a power supply, and a reset signal is input into its gate. An n-channel transistor has its source connected to a terminal of a grounded fuse, its drain connected to the drain of the first p-channel transistor, and the reset signal is input into its gate. A second p-channel transistor has its drain connected to the drains of the first p-channel transistor and the n-channel transistor, and its source connected to the power supply. The on-resistance of the second p-channel transistor is higher than that of the n-channel transistor. An inverter has its input terminal connected to the drains of the first p-channel transistor and the n-channel transistor, and its output terminal, where a repair signal is output, connected to the gate of the second p-channel transistor.
Inventors
- 👤 Koji Goto
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-06 04:20
CPC Classifications
G; G11; G11C; G11C29/00; G11C29/70; G11C29/78; G11C29/785; G11C17/00; G11C17/14; G11C17/18
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
194 words
A repair signal generating circuit comprising: a power supply; a first p-channel transistor having a source, a gate, and a drain, wherein said source is connected to said power supply, and a reset signal is input into said gate; a fuse having a grounded first terminal; an n-channel transistor, having a source, a gate, and a drain, wherein said source is connected to a second terminal of said fuse, the reset signal is input into said gate, and said drain is connected with said drain of said first p-channel transistor; a second p-channel transistor having a source, a gate, and a drain, wherein said source is connected to said power supply, said drain is connected to said drains of said first p-channel transistor and said n-channel transistor, said second p-channel transistor having an on-resistance higher than that of said n-channel transistor; and an inverter having an input terminal and an output terminal, wherein said input terminal is connected to said drains of said first p-channel transistor and said n-channel transistor, and said output terminal is connected to said gate of said second p-channel transistor, said inverter outputting a repair signal from said output terminal.
Claim 2
Dependent Claim
194 words
A repair signal generating circuit comprising: a power supply; a first p-channel transistor having a source, a gate, and a drain, wherein said source is connected to said power supply, and a reset signal is input into said gate; a fuse having a grounded first terminal; an n-channel transistor, having a source, a gate, and a drain, wherein said source is connected to a second terminal of said fuse, the reset signal is input into said gate, and said drain is connected with said drain of said first p-channel transistor; a second p-channel transistor having a source, a gate, and a drain, wherein said source is connected to said power supply, said drain is connected to said drains of said first p-channel transistor and said n-channel transistor, said second p-channel transistor having an on-resistance higher than that of said n-channel transistor; and an inverter having an input terminal and an output terminal, wherein said input terminal is connected to said drains of said first p-channel transistor and said n-channel transistor, and said output terminal is connected to said gate of said second p-channel transistor, said inverter outputting a repair signal from said output terminal.
Claim 3
Dependent Claim
30 words
The repair signal generating circuit according to claim 1 , including a capacitor connected between said power supply and said drains of said first p-channel transistor and said n-channel transistor.
Claim 4
Dependent Claim
51 words
The repair signal generating circuit according to claim 1 further comprising a delay circuit for delaying the reset signal representing a reset release, wherein the reset signal representing the reset release is delayed and output to circuits of a semiconductor integrated circuit on which said repair signal generating circuit is mounted.
Claim 5
Dependent Claim
47 words
The repair signal generating circuit according to claim 3 , wherein said delay circuit comprises a plurality of stages of first flip-flop circuits and the reset signal representing the reset release is delayed and output in synchronization with a system clock supplied to the semiconductor integrated circuit.
Claim 6
Dependent Claim
113 words
The repair signal generating circuit according to claim 4 further comprising: a second flip-flop circuit which latches and outputs the repair signal output by said inverter in response to reset signals output by said plurality of first flip-flop circuits; a third flip-flop circuit which further delays the reset signals output by said plurality of stages of first flip-flop circuits; and a reset signal input circuit which produces an AND result of an inversion of the reset signal output by said third flip-flop circuit and the reset signal to be input into said repair signal generating circuit, and outputs the AND result to said gates of said first p-channel transistor and said n-channel transistor.
References Cited (Backward Citations)
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2004-05-21 | 2004-11-20 | 2005-05-22 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2008-05-21 | 2008-11-20 | 2009-05-22 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2012-05-21 | 2012-11-20 | 2013-05-22 | $7700.00 | Window Closed / Lapsed |