US5297086A
Expired / Lapsed
US
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Method for initializing redundant circuitry
Assignee: Texas Instruments Inc
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Filing: 1992-05-27
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Granted: 1994-03-22
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Expires: 2012-05-27
Abstract
Abstract A method for initilizing redundant circuitry of a semiconductor memory device is disclosed. The method comprises sectioning the redundant circuitry and applying an initilizing pulse to each section of redundant circuitry at a different time during power up. Such a method is useful setting the redundant circuits in a dynamic random access memory device.
Inventors
- 👤 Takumi Nasu
- 👤 Hugh P. McAdams
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-06 08:41
CPC Classifications
G; G11; G11C; G11C29/00; G11C29/70; G11C29/78; G11C29/83; G06; G06F; G06F11/00; G06F11/22; G06F11/2273; G11C29/04; G11C29/50; G11C29/781
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
121 words
In a semiconductor memory device having an array of memory cells and redundant array circuits, a method to reduce peak current power drawn by in the redundant array circuits when electrical power is applied to the semiconductor device comprising the steps of: producing a power up signal in response to sensing application of power to the device; dividing the redundant array circuits into plural redundant array groups; generating a timed sequence of plural activation pulses for the respective plural redundant array groups in response to receipt of the power up signal; and supplying the activation pulses to the respective redundant array groups so that each group receives power in timed sequence to avoid high peak current into the redundant array circuits.
Claim 2
Dependent Claim
121 words
In a semiconductor memory device having an array of memory cells and redundant array circuits, a method to reduce peak current power drawn by in the redundant array circuits when electrical power is applied to the semiconductor device comprising the steps of: producing a power up signal in response to sensing application of power to the device; dividing the redundant array circuits into plural redundant array groups; generating a timed sequence of plural activation pulses for the respective plural redundant array groups in response to receipt of the power up signal; and supplying the activation pulses to the respective redundant array groups so that each group receives power in timed sequence to avoid high peak current into the redundant array circuits.
Claim 3
Dependent Claim
42 words
The method of claim 1 in which the array of memory cells is divided into a certain number of groups and the step of dividing the redundant array circuits includes dividing the redundant array circuits into the same certain number of groups.
Claim 4
Dependent Claim
38 words
The method of claim 1 in which the redundant array circuits include redundant row circuits and redundant column circuits, and the step of supplying includes supplying an activation signal to each redundant row circuit and redundant column circuit.
Claim 5
Dependent Claim
33 words
The method of claim 3 in which the generating includes generating the activation signals for the redundant column circuits from intermediate signals used to generate the activation signals for the row redundant circuits.
Claim 6
Dependent Claim
29 words
The method of claim 3 in which the generating includes combining the pulse widths of plural activation signals to generate fewer activation signals than the number of array groups.
References Cited (Backward Citations)
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1997-03-21 | 1997-09-20 | 1998-03-22 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-03-21 | 2001-09-20 | 2002-03-22 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-03-21 | 2005-09-20 | 2006-03-22 | $7700.00 | Window Closed / Lapsed |